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LE58083ABGC 参数 Datasheet PDF下载

LE58083ABGC图片预览
型号: LE58083ABGC
PDF下载: 下载PDF文件 查看货源
内容描述: [PCM Codec, A/MU-Law, 1-Func, CMOS, PBGA121, GREEN, M0-219B, LFBGA-121]
分类和应用: PC电信电信集成电路
文件页数/大小: 95 页 / 915 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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Le58083  
Data Sheet  
Master Clock  
(See Figure 16 for the Master Clock timing diagram.)  
No.  
37  
38  
39  
40  
41  
Symbol  
JMCY  
Parameter  
Master clock jitter  
Min  
Typ  
Max  
50  
Unit  
Notes  
6
tMCR  
tMCF  
tMCH  
tMCL  
Rise time of clock  
15  
Fall time of clock  
15  
ns  
MCLK HIGH pulse width  
MCLK LOW pulse width  
48  
48  
Auxiliary Output Clocks  
No.  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Chopper clock frequencyCHP = 0  
256  
fCHP  
42  
kHz  
7
CHP = 1  
292.57  
DCCHP  
fE1  
tE1  
42A  
43  
44  
Chopper clock duty cycle  
E1 output frequency (CMODE = EE1 = 1)  
E1 pulse width (CMODE = EE1 = 1)  
50  
4.923  
31.25  
%
kHz  
µs  
7
7
7
Notes:  
1. If CFAIL = 1 (Command 55h), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating all channels or  
switching them to default coefficients; otherwise, a chip select off time of 25 µs is required.  
2. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.  
3. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock frequency is 8.192  
MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 128  
kHz in Companded state and 256 kHz in Linear state, PCM Signaling state, or double PCLK state. The minimum PCM clock rates should  
be doubled for parts with only one PCM highway in order to allow simultaneous access to all four channels.  
4. TSC is delayed from FS by a typical value of NtPCY, where N is the value stored in the time/clock-slot register.  
5. tTSO is defined as the time at which the output achieves the Open Circuit state.  
6. PCLK and MCLK are required to be integer multiples of the frame sync (FS) frequency. Frame sync is expected to be an accurate 8 kHz  
pulse train. If PCLK or MCLK has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met.  
7. Phase jumps of 81 ns will be present when the master clock frequency is a multiple of 1.544 MHz.  
22  
Zarlink Semiconductor Inc.  
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