Le58083
Data Sheet
SWITCHING CHARACTERISTICS
The following are the switching characteristics over operating range (unless otherwise noted). Min and max values are valid for
all digital outputs with a 115 pF load, except CD1–C7 with a 30 pF load. (See Figure 11 and Figure 12 for the microprocessor
interface timing diagrams.)
Microprocessor Interface
No.
1
Symbol
tDCY
Parameter
Data clock period
Min
122
48
Typ
Max
Unit
Note
tDCH
tDCL
tDCR
tDCF
2
Data clock HIGH pulse width
Data clock LOW pulse width
Rise time of clock
3
48
4
25
5
Fall time of clock
25
tICSS
tICSH
tICSL
tICSO
tIDS
tDCY –10
tDCH –20
6
Chip select setup time, Input mode
Chip select hold time, Input mode
Chip select pulse width, Input mode
Chip select off time, Input mode
Input data setup time
30
0
7
8tDCY
8
9
2500
25
1
10
11
12
13
14
15
16
17
18
19
20
21
ns
tIDH
Input data hold time
30
tOLH
SLIC device output latch valid
Chip select setup time, Output mode
Chip select hold time, Output mode
Chip select pulse width, Output mode
Chip select off time, Output mode
Output data turn on delay
Output data hold time
2500
tOCSS
tOCSH
tOCSL
tOCSO
tODD
tODH
tODOF
tODC
tRST
tDCY –10
tDCH –20
30
0
8tDCY
2500
3
1
2
50
Output data turn off delay
Output data valid
50
50
Reset pulse width
50
µs
PCM Interface
PCLK not to exceed 8.192 MHz.
Pull-up resistors to VCCD of 240 Ω are attached to TSCA and TSCB. (See Figure 13 through Figure 15 for the PCM interface
timing diagrams.)
No.
22
23
24
25
26
27
28
30
31
32
33
34
35
36
Symbol
tPCY
Parameter
PCM clock period
Min.
122
48
Typ
Max
Unit
Note
3
tPCH
tPCL
tPCF
tPCR
tFSS
tFSH
tTSD
tTSO
tDXD
tDXH
tDXZ
tDRS
tDRH
PCM clock HIGH pulse width
PCM clock LOW pulse width
Fall time of clock
48
15
15
Rise time of clock
tPCY–30
FS setup time
25
50
5
FS hold time
ns
Delay to TSC valid
80
80
70
70
70
4
Delay to TSC off
5
4,5
PCM data output delay
PCM data output hold time
PCM data output delay to High-Z
PCM data input setup time
PCM data input hold time
5
5
5
25
5
21
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
