GP2021
CONTENTS
TYPICAL GPS RECEIVER
PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
12-Channel Correlator
Tracking Modules
Page
3
4
7
7
8
11
11
12
12
14
15
15
21
Page
CONTROLLING THE GP2021
24
DETAILED DESCRIPTION OF REGISTERS
28
GP2021 Register Map
28
Correlator Registers
30
Tracking Channel Registers
30
Peripheral Functions Registers
43
Real Time Clock and Watchdog
43
DUART
43
SYSTEM CONTROL
44
45
GENERAL CONTROL
47
ELECTRICAL CHARACTERISTICS
TIMING CHARACTERISTICS
51
PERIPHERAL FUNCTIONS
Dual UART
Real Time Clock (RTC) and Watchdog
Power and Reset Control
Discrete l/O
Digital System Test Interface
MICROPROCESSOR INTERFACE
SOFTWARE REQUIREMENTS
Absolute Maximum Ratings
60
61
41
40
These are not the operating conditions, but are the absolute
limits which if exceeded, even momentarily, may cause
permanent damage. To ensure sustained correct operation
the device should be used within the limits given under
Electrical Characteristics. It is essential for both V
DD
and
V
SS
to be present before input signals are applied.
Supply voltage (V
DD
)
V
SS
20·3V
to
16V
Input voltage (any input pin)
V
SS
20·3V
to V
DD
10·3V
Output voltage (any output pin) V
SS
20·3V
to V
DD
10·3V
Storage temperature
255°C
to
1150°C
GP2021
PIN 1 IDENT
80
1
20
21
GQ80
Figure 2 Pin connections - top view
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
MULTI_FN_IO
POWER _GOOD
NRESET_OP
NARMSYS
XIN
XOUT
TXA
TXB
RXA
RXB
NROM/NC
NEEPROM/NC
NSPARE_CS/NC
V
DD
V
SS
NRAM/NC
NW0/NC
NW1/NC
NW2/NC
NW3/NC
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Description
NRD/NC
ARM_ALE/NC
DBE/NC
ACCUM_INT
MEAS_INT
NBW/WRPROG
NMREQ/DISCIP2
NOPC/NINTELMOT
NRW/DISCIP3
MCLK/NC
ABORT MICRO_CLK
DISCIO
A22/READ
V
DD
V
SS
A21/NCS
A20/WREN
A9
A8
A7
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Description
A6
A5
A4
A3
A2
A1/ALE_IP
A0/NRESET_IP
D0
D1
D2
D3
D4
D5
D6
V
DD
V
SS
D7
D8
D9
D10
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Description
D11
D12
D13
D14
D15
PLL_LOCK
V
DD
DISCOP
V
SS
CLK_T
CLK_I
V
SS
SAMPCLK
V
DD
NBRAM / DISCIP4
SIGN0
MAG0
SIGN1
MAG1
DISCIP1
Table 1 Pin assignments
2
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
