GP2021
GPS 12-Channel Correlator
Features
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DS4077
Issue 3.2
April 2001
Ordering Information
GP2021/IG/GQ1N (Trays)
GP2021/IG/GQ1Q (Tape and Reel)
12 Fully Independent Correlation Channels
On-Chip Dual UART and Real Time Clock
Compatible with most 16- and 32-bit Microprocessors
Memory Control Logic for ARM60 Microprocessor
Low Voltage, Low Current Power-Down Mode
Power Dissipation 150mW Typical
Compatible with GP2015 and GP2010 RF Front Ends
Battery Backup Voltage 2.2V (min)
Description
The GP2021 is a 12-channel C/A code baseband correlator
for use in NAVSTAR GPS satellite navigation receivers.
The GP2021 complements the GP2015 and GP2010 C/A
code RF downconverters available from Zarlink
Semiconductor.
The GP2021 is compatible with most 16-bit and 32-bit
microprocessors, especially those from Motorola and Intel,
with additional on-chip support for the ARM60 32-bit RISC
processor. When the ARM60 is used, the on-chip memory
management functions allow implementation of a full GPS
receiver with minimal external logic.
The GP2021 allows individual channel de-activation, for
systems not requiring full 12-channel operation, to save
power and processor loading. Receiver power may be
further conserved by reducing the supply voltage to 2.2V
under battery backup; all system functions are then
disabled but the 32.768kHz oscillator and Real Time Clock
are maintained for the microprocessor to estimate satellite
visibility at power-on to reduce signal acquisition time.
RXA TXA RXB TXB
XIN
XOUT
Applications
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GPS Navigation Systems
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GPS Geodetic Receivers
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Time Transfer Receivers
Related Global Positioning Products
Part
GP2015
GP2010
Description
GPS receiver RF front end
(48-lead TQFP package)
GPS receiver RF front end
(44-lead PQFP package)
GPS ORION 12 Channel
GPS Receiver Reference
Design
GPS2000 GPS Receiver
Hardware Design
ACCUM_INT
MEAS_INT
Data ref.
DS4374
DS4056
DS3553
AN4808
P60ARM-B 32 bit RISC microprocessor
App. Note
App. Note
AN4855
D<15:0>
SIGN, MAG
SAMPCLK
CLK_T, CLK_I
DUAL UART
GPS
12-CHANNEL
CORRELATOR
CONTROL BUS
DATA BUS
REAL TIME CLOCK
NARMSYS
POWER_GOOD
PLL_LOCK
POWER AND
RESET
CONTROL
MICRO_CLK
MICROPROCESSOR INTERFACE
ARM SYSTEM
STANDARD INTERFACE
A<9:0>
NINTEL/ MOT
WRPROG
NRESET_I/P
NRESET_O/P
A<22:20>
ARM60
MEMORY
INTERFACE INTERFACE
ALE_I/P NCS
WREN READ
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
