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GP2015/IG/FP1Q 参数 Datasheet PDF下载

GP2015/IG/FP1Q图片预览
型号: GP2015/IG/FP1Q
PDF下载: 下载PDF文件 查看货源
内容描述: [SPECIALTY TELECOM CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48]
分类和应用: 电信电信集成电路
文件页数/大小: 24 页 / 212 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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GP2015
ABSOLUTE MAXIMUM RATINGS
(Non-simultaneous)
Max. Supply Voltage
7V
Max. RF Input
+15dBm
Max. voltage on any pin
V
CC
/V
DD
+ 0.5V
except LD (pin 21) and PReset (pin 9), which are 5.5V Min.
voltage on any pin
V
EE
- 0.5V
Storage Temperature
-65°C to +150°C
Operation Junction Temperature
-40°C to +150°C
10MHz Reference Input
1.5V pk -pk
IF STRIP
The input signal to the GP2015 is the GPS L1 signal
received via an antenna and a suitable LNA. The L1 input is
a spread spectrum signal at 1575.42MHz with 1.023Mbps
BPSK modulation. The signal level at the antenna is about
-130dBm, spread over a 2.046MHz bandwidth, so the wanted
signal is actually buried in noise. The high RF input
compression point of the GP2015 means that with subsequent
IF filtering it is possible to reject large out of band jamming
signals, in particular 900MHz as used by mobile
telephones.The on-chip PLL generates the first local-oscillator
frequency at 1400MHz. The output of the front-end mixer
(Stage 1) at 175.42 MHz can then be filtered before being
applied to the second stage. The double-balanced stage 1
mixer outputs are open-collectors, and require external dc
bias to V
CC
.
The second stage contains further gain and a mixer
with a local oscillator signal at 140 MHz giving a second IF at
35.42 MHz. The second stage mixer is also double-balanced
with open-collector outputs requiring external dc bias to V
CC
.
The signal from stage 2 is passed through an external
filter with a 1dB bandwidth of 1.9MHz. The performance of
this filter is critical to system performance and it is
recommended that a SAW filter is used (part number
SAFJA35M4WC0Z00 , available from Murata). The output of
the filter then feeds the main IF amplifier. This includes 2
AGC amplifiers and a third mixer with a local oscillator signal
at 31.111 MHz giving a final IF at 4.309 MHz. There is an on-
chip filter after the third mixer which provides filtering centred
on 4.309 MHz. The IF output, which has 1kΩ output
impedance, is provided for test purposes. All of the signals
within the IF amplifier are differential including the filter inputs
ESD PROTECTION
The GP2015 device is static sensitive. The most
sensitive pins withstand a 750V test by the human body
model. Therefore, ESD handling precautions are essential to
avoid degradation of performance or permanent damage to
this device.
PRODUCT DESCRIPTION
The GP2015 receives the 1575.42MHz signal
transmitted by GPS satellites and converts it to a 4.309MHz
IF, using triple down-conversion. The 4.309MHz IF is sampled
to produce a 2-bit digital output. If the GP2015 is used in
conjunction with the GP2021 correlator, then the GP2021
provides a sampling clock of 5.714MHz. This converts the IF
to a 1.405MHz 2-bit digital output at TTL levels.
The GP2015 can operate from a single supply from
+3V (nominal) to +5V (nominal).
A block diagram of the circuit is shown in figure 2.
175.42MHz FILTER
(37,38)
(40,41)
35.42MHz FILTER
(44,45)
(47,48)
AGC CAPACITOR
(23)
(24)
(32)
RF Input
L1
(1575.42MHz)
FRONT
END
MIXER
1.400GHz
2nd
STAGE
MIXER
140MHz
AGC
AGC
3rd
STAGE
MIXER
31.11MHz
4.3MHz
FILTER
(1)
IF Output
(4.309MHz)
VCO
VOLTAGE
REGULATOR
(2)
÷5
÷5
÷2
AGC
CONTROL
+Vr
EXTERNAL
LOOP
FILTER
(3)
PLL
LOOP
FILTER
÷7
÷9
+1.21V
-Vr
_
+
÷4
PLL LOCK
LOGIC O/P
(LD)
(21)
PHASE
DETECTOR
POWER-ON
RESET
1.400GHz
PHASE-
LOCKED
LOOP
SIGN
O/P
LATCH
POWER
CONTROL
(15)
SIGN
TTL O/P
PLL REF I/P
10MHz (REF 2)
(27)
PLL
REFERENCE
OSCILLATOR
MAG
O/P
LATCH
(14)
MAG
TTL O/P
(28)
REF 1 I/P
(FOR USE WITH
CRYSTAL REF
ONLY)
A -> D
CONVERTER
(16,17)
(20)
(8)
(19)
(9)
(11)
SAMPLE
CLOCK I/P (CLK)
(5.71MHz TTL)
40MHz CLOCK O/P
(FOR CORRELATOR
CHIP)
(OPCIK +/-)
(TEST)
POWER-ON
REFERENCE
I/P
(PREF)
POWER
DOWN I/P
(PDn)
POWER-ON
RESET O/P
(PRESET)
Figure 2 - Block diagram of GP2015
2