P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
EA218
6+2 Ports 10Mb Ethernet Access Controller
1.2 Pin Assignment (Preliminary)
Note:
#
Input
Active low signal
Input signal
In-ST
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Input with 5V Tolerance
Output
Out-OD
I/O-TS
I/O-OD
5VT
ꢁ
ꢂ
ꢃ
Output signal with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
Max
Pin No(s).
Symbol
Type
Name and Functions
I
OL / IOH
Management Bus Interface
J25,K26,L24,K25,L26,
M24,L25,M26,N24,M25,
P24,N26,N25,R24,P26, P25
P_D[15:0]
TTL I/O-TS (5VT)
16mA Management Bus – Data Bit [15:0]
Management Bus – Address Bit [11:1]
C26,D24,C25,E24,D26,
D25,F24,E26,E25,G24, F26
P_A[11:1]
TTL In (5VT)
F25
H25
J24
G25
G26
H26
J26
K24
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
TTL In (5VT)
TTL In (5VT)
Management Bus – Address Strobe
Management Bus – Read/Write Control
16mA Management Bus – Data Ready
16mA Management Bus – 16 bit Data Bus
Management Bus – Chip Select
TTL Out-OD
TTL Out-OD
TTL In (5VT)
P_INT
ꢁ CMOS Output
TTL In-ST (5VT)
TTL In (5VT)
4mA
Management Bus – Interrupt Request
Management Bus – Master Reset
Management Bus – Bus Clock
P_RST#
P_CLK
XpressFlow Bus Interface
C23,A23,B22,C22,A22
S_D[31:27] /
P_C[0:4]
CMOS I/O-TS
CMOS I/O-TS
12 mA XpressFlow Bus – Data Bit [31:27] or Manage-
ment Bus Interface Configuration bit [0:4]
B21,D20,C21,A21,B20,
A20,C20,B19,A19,C19,
B18,A18,B17,C18,A17,
D17,B16,C17,A16,B15,
A15,C16,B14,D15,A14,
C15,B13
S_D[26:0]
12mA XpressFlow Bus – Data Bit [26:0]
B12
A12
C14
C13
B23
A24
B24
A13
D13
S_MSGEN#
S_EOF#
S_IRDY
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-OD
CMOS I/O-OD
CMOS Output
CMOS Input
CMOS Input
CMOS Input
12 mA XpressFlow Bus – Message Envelope
12mA XpressFlow Bus – End of Frame
12 mA XpressFlow Bus – Initiator Ready
12 mA XpressFlow Bus – Target Abort
12mA XpressFlow Bus – High Priority Request
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
4mA
XpressFlow Bus – Bus Request to SC201
XpressFlow Bus – Bus Grant from SC201
XpressFlow Bus – Bus Overload
XpressFlow Bus – Clock
© 1998 Zarlink Semiconductor, Inc.
4
Rev. 2.1- February, 1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
