P
R
E
L
I M
I N
A
R
Y
D A
T
A
S
H E
E
T
XpressFlow-2001 Series –
Ethernet Switch Chip-set
Pin No(s).
Symbol
EA-224
4-Port 10/100M Ethernet Access Controller
Type
Max
I
OL
/ I
OH
Name & Functions
Control Buffer Memory Interface
M4,N2,L3,M1,M2,L1,K3, L_D[31:0]
TTL I/O-TS
L2,K4,K1,J3,K2,J1,J2,
H3,H1,H2,G3,G1,G2,F1,
F3,F2,E1,E3,E2,D1,D3,
D2,C1,C2,B1
CMOS Output
A6,B6,C8,A7,D8,D7,C9, L_A[18:2]
A8,B8,A9,C10,B9,D10,
A10,C11,B10,A11
C7
L_A[19] /
CMOS Output
L_OE[3]#
D5,A5,A3
L_OE[2:0]#
CMOS Output
D7,E4,B5,C4
L_WE[3:0]#
CMOS Output
C6,B4,A4,C5
L_BWE[3:0]# CMOS Output
B3
G4
L_ADSC#
L_CLK
CMOS Output
CMOS Output
CMOS Output
@
8mA
Local Memory Bus – Data Bit [31:0]
8mA
Local Memory Bus – Address Bit [17:2]
8mA
2mA
2mA
8mA
8mA
8mA
4mA
4mA
Local Memory Bus – Address Bit [19] or
Memory Read Chip Select [3]
Local Memory Read Chip Select [2:0]
Local Memory Write Chip Select [3:0]
Local Memory Byte Write Enable, Byte
[3:0]
Local Memory Controller Address Status
Local Memory Clock input
MII Management Data Clock – (common
for all MII Ports – Port [1:0])
MII Management Data I/O – (common for
all MII Ports – Port [1:0]))
Port [3:0] – MII Receive Data Bit [3]
Port [3:0] -- Receive Data Bit [2]
Port [3:0] -- Receive Data Bit [1]
Port [3:0] -- Receive Data Bit [0]
Port [3:0] -- Receive Data Valid
Port [3:0] -- Receive Clock
Port [3:0] -- Receive Error
Port [3:0] -- Transmit Error
Port [3:0] -- Transmit Clock
Port [3:0] -- Transmit Enable
Port [3:0] -- Transmit Data Bit [3]
Port [3:0] -- Transmit Data Bit [2]
Port [3:0] -- Transmit Data Bit [1]
Port [3:0] -- Transmit Data Bit [0]
Port [3:0] -- Collision Detected
Port [3:0] -- Carrier Sense
Port [3:0] -- Link Status
Fast Ethernet Access Port [3:0]
T24
M_MDC
R26
AB2,U25,AE26,AF5
AB1,V24,AD25,AE6
AA3,U26,AD26,AD6
AC2,T25
AC25,AF6
Y3,V26,AF24,AD5
AC1,U24
AC24,AE7
AA1,V25,AD23,AE5
AA2,W24,AE24,AF4
W2,AA25,AE22,AD1
W1,AA24,AF22,AF2
V3,AA26,AD21,AE3
Y2,Y26,AE23,AF3
W3,W26,AD22,AD4
Y1,W25,AF23,AE4
V1,AB26
AD20,AC3
U3,AB24
AF21,AD2
V2,AB25
AE21,AB3
M_MDIO
@
@
M[3:0]_RXD[1] TTL In (5VT)
@
M[3:2]_RXD[0] TTL In (5VT)
@
M[1:0]_RXD[0] TTL In (5VT)
M[3:0]_RXDV TTL In (5VT)
@
M[3:2]_RXC
TTL In (5VT)
@
M[1:0]_RXC
M[3:0]_RXER
M[3:0]_TXER
M[3:0]_TXC
M[3:0]_TXEN
M[3:0]_TXD[3]
M[3:0]_TXD[2]
M[3:0]_TXD[1]
M[3:0]_TXD[0]
M[3:2]_COL
M[1:0]_COL
M[3:2]_CRS
M[1:0]_CRS
M[3:2]_LNK
TTL In (5VT)
CMOS Output
TTL In (5VT)
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
CMOS I/O-TS
4mA
4mA
4mA
4mA
4mA
4mA
TTL IO-TS
(5VT)
M[3:0]_RXD[3] TTL In (5VT)
M[3:0]_RXD[2] TTL In (5VT)
?
M[1:0]_LNK
?
T_MODE
@
@
@
Test Facility
A25
N1,M3,P2,P1,N3,R2,P3, T_D[15:10]
R1,T2,R3,T1,R4,U2,T3,
U1,U4
A
CMOS Output
@
2mA
4mA
Test Pin – Set Test Mode upon Reset,
and provides test status output during
test mode
Test Pins – Reserved for internal use
only
© 1997 Zarlink Semiconductor Inc.
Page: 5
Rev. 4.0 –December, 1997
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
