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XpressFlow-2001 Series –
Ethernet Switch Chip-set
EA-224
4-Port 10/100M Ethernet Access Controller
4. FUNCTIONAL DESCRIPTION
4.1 Local Memory (Local Buffer Memory) Interface
Use industry standard Synchronous Burst Mode SRAM up to 1M bytes
32k x 32, 64k x 32, 128k x 32, or 256k x 32
Provides 4 individual
Byte Write Enable
controls ( L_BWE[3:0]# )
Provides separate Read and Write Chip Selects ( L_OE[3:0]# and L_WE[3:0]# ) for each memory chip
Supports back to back Read or Write operations across memory chips
4.1.1 Pin Description
Symbol
L_D[31:0]
L_A[18:2]
Type
Name & Functions
@
TTL
Local Memory Data Bus Bit [31:0]
– a 32-bit synchronous data bus.
I/O-TS
CMOS
Local Memory Address Bus Bit [18:2]
– Bit [18:2] of a synchronous
Output address bus. The memory address is sampled when L_CS# is enabled
and L_ADSC# is asserted.
CMOS
Local Memory Address Bus Bit [19]
or
Local Memory Read Chip
Output
Select [3]
– Depends on memory configuration, this pin can be used as
the Local Memory Address Bit [19] or as the Local Memory Read Chip
Select [3].
CMOS
Local Memory Read Chip Select [2:0]
– allows up to read one of the 4
Output banks of memory.
CMOS
Local Memory Write Chip Select [3:0]
– allows up to write one of the 4
Output banks of memory.
CMOS
Local Memory Byte Write Enable [3:0]
– use to write individual bytes.
Output
CMOS
Local Memory Controller Address Status
– to load a new address.
Output
CMOS
Local Memory Clock
– a synchronous clock to memory devices.
Output
L_A[19] /
L_OE[3]#
L_OE[2:0]#
L_WE[3:0]#
L_BWE[3:0]#
L_ADSC#
L_CLK
Note:
@
These pins have weak internal pull up resistors (50k to 100k Ohms each).
© 1997 Zarlink Semiconductor Inc.
Page: 8
Rev. 4.0 –December, 1997
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
