R
QPRO XQ4000E/EX QML High-Reliability FPGAs
Bound
Bound
Scan
Pin Description
PG191 CB196
Scan
457
460
463
446
469
472
475
478
481
484
-
Pin Description
PG191 CB196
I/O
V5
V4
U5
T6
V3
V2
U4
T5
U3
T4
V1
R4
U2
R3
T3
U1
-
P136
P137
P138
T139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
I/O
I/O_(A6)
I/O_(A7)
GND
K1
K2
K3
K4
J4
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
53
56
59
-
I/O
I/O
I/O
I/O_(D1)
VCC
-
I/O_(RCLK-/BUSY/RDY)
I/O_(A8)
I/O_(A9)
I/O
J3
62
65
68
71
74
77
80
83
86
89
-
I/O
J2
I/O
J1
I/O_(D0*_DIN)
I/O
H1
H2
H3
G1
G2
F1
E1
G3
F2
D1
C1
E2
F3
D2
-
SGCK4_(DOUT*_I/O)
I/O
CCLK
I/O
VCC
-
I/O_(A10)
I/O_(A11)
I/O
TDO
-
GND
-
I/O_(A0*_WS)
2
I/O
PGCK4_(I/O*_A1)
5
GND
(1)
-
P152
P153
P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
-
I/O
92
96
98
101
104
107
-
I/O
P3
R2
T2
N3
P2
T1
R1
N2
M3
P1
N1
M2
M1
L3
L2
L1
8
I/O
I/O
I/O_(CS1*_A2)
I/O_(A3)
I/O
11
14
17
20
23
26
29
-
I/O
I/O
I/O_(A12)
I/O_(A13
-
(1)
I/O
P192
P193
P194
P195
P196
I/O
I/O
E3
C2
B2
D3
113
116
119
-
I/O
I/O_(A14)
SGCK1(A15*I/O)
VCC
GND
I/O
32
35
38
41
44
47
50
Notes:
1. Indicates unconnected package pins.
I/O
I/O_(A4)
I/O_(A5)
I/O
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
I/O
Additional XQ4010E Package Pins
I/O
CB196
Notes:
1. Indicates unconnected package pins.
No Connect Pins
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
P5
P54
-
P103
-
P152
-
Boundary Scan Bit 1 = TD0.0
P192
Boundary Scan Bit 487 = BSCAN.UPD
34
www.xilinx.com
1-800-255-7778
DS021 (v2.2) June 25, 2000
Product Specification
XILINX [ XILINX, INC ]
