R
Spartan-II FPGA Family: Pinout Tables
Additional XC2S200 Package Pins
XC2S200 Device Pinouts (Continued)
XC2S200 Pad Name
PQ208
Bndry
Scan
Function
GND
Bank
PQ208
FG256
GND*
A5
FG456
GND*
B7
Not Connected Pins
P55
P56
-
-
-
-
-
P198
-
11/02/00
I/O
0
0
0
0
-
P199
188
191
197
200
-
I/O, VREF
I/O
P200
C6
E8
FG256
-
-
D8
VCCINT Pins
I/O
P201
B5
C7
C3
M5
C14
M12
D4
N4
D13
N13
E5
P3
E12
P14
GND
I/O
-
GND*
D6
GND*
D7
0
0
0
0
0
0
-
203
206
209
212
215
-
V
V
V
V
V
V
V
V
CCO Bank 0 Pins
I/O
-
-
B6
E8
E9
H11
J11
L9
F8
F9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
-
-
A5
CCO Bank 1 Pins
I/O
P202
P203
-
A4
D6
-
-
I/O, VREF
VCCO
B4
C6
CCO Bank 2 Pins
VCCO
Bank 0* Bank 0*
VCCO
H12
J12
M9
M8
J6
-
-
CCO Bank 3 Pins
GND
I/O
-
-
GND*
E6
D5
-
GND*
B5
-
-
-
0
0
0
0
0
-
P204
218
221
224
230
233
-
CCO Bank 4 Pins
I/O
-
E7
-
-
I/O
-
A4
CCO Bank 5 Pins
I/O
-
-
E6
L8
-
-
I/O, VREF
GND
I/O
P205
A3
GND*
C5
-
B4
CCO Bank 6 Pins
-
GND*
A3
J5
-
-
0
0
0
0
-
-
236
239
242
248
-
CCO Bank 7 Pins
I/O
-
B3
H5
H6
-
-
I/O
-
-
D5
GND Pins
I/O
P206
P207
P208
B3
C4
VCCO
Bank 0* Bank 0*
VCCO VCCO
Bank 7* Bank 7*
C5
A1
F10
G10
J7
A16
F11
G11
J8
B2
G6
H7
J9
B15
G7
F6
G8
H9
K6
L6
F7
G9
H10
K7
TCK
VCCO
C4
0
VCCO
-
H8
J10
K11
R15
VCCO
7
P208
-
K8
K9
K10
R2
L7
04/18/01
L10
L11
T1
T16
Not Connected Pins
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx PCI
cores.
P4
R4
-
-
-
-
2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*,
VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*,
VCCO Bank 6*, VCCO Bank 7* are internally bonded to
independent ground or power planes within the package.
3. See "VCCO Banks" for details on VCCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
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XILINX [ XILINX, INC ]
