R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Ordering Information
Example: XCV300E-6PQ240C
Device Type
Temperature Range
C = Commercial (Tj = 0 C to +85 C)
I = Industrial (Tj = -40 C to +100 C)
Speed Grade
(-6, -7, -8)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
DS022_043_072000
Figure 1: Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
7/10/00
1.3
1.4
1.5
Updated pinout tables, VCC page 20, and corrected Figure 20.
Correction to table on p. 22.
•
Numerous minor edits.
•
•
•
•
•
•
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
Min values added to Virtex-E Electrical Characteristics tables.
8/1/00
1.6
1.7
9/20/00
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT
pins in Table ~ (Module 4).
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Module 1 of 4
4
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DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
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