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XCV1600E-7FG900C 参数 Datasheet PDF下载

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型号: XCV1600E-7FG900C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -E 1.8 V现场可编程门阵列 [Virtex-E 1.8 V Field Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 5 页 / 89 K
品牌: XILINX [ XILINX, INC ]
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R
Virtex-E 1.8 V Field Programmable Gate Arrays  
Table 2: Performance for Common Circuit Functions  
resources. The abundance of routing resources permits the  
Virtex-E family to accommodate even the largest and most  
complex designs.  
Function  
Register-to-Register  
Adder  
Bits  
Virtex-E (-7)  
Virtex-E FPGAs are SRAM-based, and are customized by  
loading configuration data into internal memory cells. Con-  
figuration data can be read from an external SPROM (mas-  
ter serial mode), or can be written into the FPGA  
(SelectMAP, slave serial, and JTAG modes).  
16  
64  
4.3 ns  
6.3 ns  
Pipelined Multiplier  
Address Decoder  
8 x 8  
4.4 ns  
5.1 ns  
The standard Xilinx Foundation Seriesand Alliance  
SeriesDevelopment systems deliver complete design  
support for Virtex-E, covering every aspect from behavioral  
and schematic entry, through simulation, automatic design  
translation and implementation, to the creation and down-  
loading of a configuration bit stream.  
16 x 16  
16  
64  
3.8 ns  
5.5 ns  
16:1 Multiplexer  
Parity Tree  
4.6 ns  
9
3.5 ns  
4.3 ns  
5.9 ns  
Higher Performance  
18  
36  
Virtex-E devices provide better performance than previous  
generations of FPGAs. Designs can achieve synchronous  
system clock rates up to 240 MHz including I/O or 622 Mb/s  
using Source Synchronous data transmission architech-  
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-  
tions, and interfaces can be implemented that operate at  
33 MHz or 66 MHz.  
Chip-to-Chip  
HSTL Class IV  
LVTTL,16mA, fast slew  
LVDS  
While performance is design-dependent, many designs  
operate internally at speeds in excess of 133 MHz and can  
achieve over 311 MHz. Table 2 shows performance data for  
representative circuits, using worst-case timing parameters.  
LVPECL  
Virtex-E Device/Package Combinations and Maximum I/O  
Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)  
XCV  
50E  
XCV  
100E  
XCV  
200E  
XCV  
300E  
XCV  
400E  
XCV  
600E  
XCV  
1000E  
XCV  
1600E  
XCV  
2000E  
XCV  
2600E  
XCV  
3200E  
CS144  
PQ240  
HQ240  
BG352  
BG432  
BG560  
FG256  
FG456  
FG676  
FG680  
FG860  
FG900  
FG1156  
94  
94  
94  
158  
158  
158  
158  
158  
158  
158  
404  
196  
176  
260  
260  
316  
316  
404  
316  
404  
404  
404  
176  
176  
284  
176  
312  
404  
444  
512  
512  
660  
660  
660  
512  
660  
700  
724  
512  
660  
512  
804  
804  
804  
DS022-1 (v2.2) November 9, 2001  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
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