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R
Virtex™-E 1.8 V
Field Programmable Gate Arrays
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DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
Features
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Fast, High-Density 1.8 V FPGA Family
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High-Performance Built-In Clock Management Circuitry
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Densities from 58 k to 4 M system gates
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Eight fully digital Delay-Locked Loops (DLLs)
130 MHz internal performance (four LUT levels)
Designed for low-power operation
Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
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Clock Multiply and Divide
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
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Highly Flexible SelectI/O+™ Technology
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Supports 20 high-performance interface standards
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Flexible Architecture Balances Speed and Density
Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
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Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Differential Signalling Support
Cascade chain for wide-input function
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LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
Differential I/O signals can be input, output, or I/O
Compatible with standard differential devices
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
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Internal 3-state bussing
LVPECL and LVDS clock inputs for 300+ MHz
clocks
IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
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Proprietary High-Performance SelectLink™
Technology
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Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
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Double Data Rate (DDR) to Virtex-E link
Web-based HDL generation methodology
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Further compile time reduction of 50%
Internet Team Design (ITD) tool ideal for
million-plus gate density designs
Sophisticated SelectRAM+™ Memory Hierarchy
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1 Mb of internal configurable distributed RAM
Up to 832 Kb of synchronous internal block RAM
True Dual-Port™ BlockRAM capability
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Wide selection of PC and workstation platforms
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SRAM-Based In-System Configuration
Unlimited re-programmability
Advanced Packaging Options
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Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
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0.8 mm Chip-scale
1.0 mm BGA
1.27 mm BGA
HQ/PQ
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Designed for high-performance Interfaces to
External Memories
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200 MHz ZBT* SRAMs
200 Mb/s DDR SDRAMs
Supported by free Synthesizable reference design
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0.18 m 6-Layer Metal Process
100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
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