R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
memory cells determine the logic functions and intercon-
nections implemented in the FPGA. The FPGA can either
actively read its configuration data from an external serial
PROM (Master Serial mode), or the configuration data can
be written into the FPGA from an external device (Slave
Serial mode).
General Overview
Spartan series FPGAs are implemented with a regular, flex-
ible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources (routing channels), and sur-
rounded by a perimeter of programmable Input/Output
Blocks (IOBs), as seen in Figure 1. They have generous
routing resources to accommodate the most complex inter-
connect patterns.
Spartan series FPGAs can be used where hardware must
be adapted to different user applications. FPGAs are ideal
for shortening design and development cycles, and also
offer a cost-effective solution for production rates well
beyond 50,000 systems per month.
The devices are customized by loading configuration data
into internal static memory cells. Re-programming is possi-
ble an unlimited number of times. The values stored in these
B-
SCAN
OSC
IOB
IOB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
IOB
IOB
Routing Channels
IOB
IOB
IOB
IOB
CLB
CLB
IOB
IOB
IOB
IOB
START
-UP
RDBK
VersaRing Routing Channels
DS060_01_081100
Figure 1: Basic FPGA Block Diagram
2
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
XILINX [ XILINX, INC ]
