R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
DIN
Bit n
Bit n + 1
T
T
T
CCL
DCC
CCD
CCLK
T
T
CCH
CCO
DOUT
(Output)
Bit n – 1
Bit n
DS060_26_080400
Symbol
Description
Min
20
0
Max
Units
ns
T
T
T
T
DIN setup
DIN hold
-
-
DCC
CCD
CCO
CCH
ns
DIN to DOUT
High time
Low time
-
30
-
ns
CCLK
40
40
-
ns
T
-
ns
CCL
F
Frequency
10
MHz
CC
Notes:
1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are
High.
Figure 26: Slave Serial Mode Programming Switching Characteristics
are in Express mode. A single combined bitstream is used
to configure the chain of Express mode devices. CCLK pins
are tied together and D0-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. Frame
data is accepted only when CS1 is High and the device’s
configuration memory is not already full. The lead device in
the chain has its CS1 input tied High (or floating, since there
is an internal pull-up). The status pin DOUT is pulled Low
after the header is received by all devices, and remains Low
until the device’s configuration memory is full. DOUT is then
pulled High to signal the next device in the chain to accept
the configuration data on the D0-D7 bus.
Express Mode (Spartan-XL only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers (Figure 27). A CCLK fre-
quency of 1 MHz is equivalent to a 8 MHz serial rate,
because eight bits of configuration data are loaded per
CCLK cycle. Express mode does not support CRC error
checking, but does support constant-field error checking. A
length count is not used in Express mode.
Express mode must be specified as an option to the devel-
opment system. The Express mode bitstream is not com-
patible with the other configuration modes (see Table 16,
page 32.) Express mode is selected by a <0X> on the Mode
pins (M1, M0).
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a large
number of devices are included in the chain, deactivate
some of the internal pull-ups, since the Low-driving DONE
pin of the last device in the chain must sink the current from
all pull-ups in the chain. The DONE pull-up is activated by
default. It can be deactivated using a development system
option.
The first byte of parallel configuration data must be available
at the D inputs of the FPGA a short setup time before the
second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge
(Figure 28).
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All Spartan-XL devices in Express mode are synchronized
to the DONE pin. User I/Os for each device become active
Pseudo Daisy Chain
Multiple devices with different configurations can be config-
ured in a pseudo daisy chain provided that all of the devices
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
29
XILINX [ XILINX, INC ]
