R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Slave Serial is the default mode if the Mode pins are left
unconnected, as they have weak pull-up resistors during
configuration.
and is captured by each FPGA when it recognizes the 0010
preamble. Following the length-count data, each FPGA out-
puts a High on DOUT until it has received its required num-
ber of data frames.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
After an FPGA has received its configuration data, it passes
on any additional frame start bits and configuration data on
DOUT. When the total number of configuration clocks
applied after memory initialization equals the value of the
24-bit length count, the FPGAs begin the start-up sequence
and become operational together. FPGA I/O are normally
released two CCLK cycles after the last configuration bit is
received.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins of
all devices in parallel, as shown in Figure 25. Connect the
DOUT of each device to the DIN of the next. The lead or
master FPGA and following slaves each passes resynchro-
nized configuration data coming from a single source. The
header data, including the length count, is passed through
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM File Formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.
Note:
M2, M1, M0 can be shorted
to V
if not used as I/O
CC
V
CC
3.3K
3.3K
3.3K
M0 M1
M2
MODE
DOUT
N/C
MODE
DIN
DOUT
DOUT
DIN
CCLK
CCLK
V
CC
Spartan
Master
Spartan
Slave
Xilinx SPROM
+5V
FPGA
Slave
3.3K
Seria
l
CLK
CCLK
V
PP
DATA
CE
DIN
LDC
INIT
CEO
PROGRAM
DONE
PROGRAM
DONE
RESET
D/P
INIT
INIT
RESET/OE
(Low Reset Option Used)
PROGRAM
DS060_25_061301
Figure 25: Master/Slave Serial Mode Circuit Diagram
28
www.xilinx.com
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
