R
Platform Flash In-System Programmable Configuration PROMS
Erase/Program (ER/PROG) Error field, IR[6:5], contains a
10
when an erase or program operation is a success;
otherwise a
01
when an erase or program operation fails.
The Erase/Program (ER/PROG) Status field, IR[4], contains
a logic 0 when the device is busy performing an erase or
programming operation; otherwise, it contains a logic 1. The
ISC Status field, IR[3], contains logic 1 if the device is
currently in In-System Configuration (ISC) mode; otherwise,
it contains logic 0. The DONE field, IR[2], contains logic 1 if
the sampled design revision has been successfully
programmed; otherwise, a logic 0 indicates incomplete
programming. The remaining bits IR[1:0] are set to
01
as
defined by IEEE Std. 1149.1.
logic 0. IR[2] is unused, and is set to '0'. The remaining bits
IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
XCFxxP Instruction Register (16 bits wide)
The Instruction Register (IR) for the XCFxxP PROM is sixteen
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in
The instruction capture pattern shifted out of the XCFxxP
device includes IR[15:0]. IR[15:9] are reserved bits and are
set to a logic 0. The ISC Error field, IR[8:7], contains a
10
when an ISC operation is a success; otherwise a
01
when
an In-System Configuration (ISC) operation fails. The
Table 6:
Platform Flash PROM Boundary Scan Instructions
Boundary-Scan Command
Required Instructions
BYPASS
SAMPLE/PRELOAD
EXTEST
Optional Instructions
CLAMP
HIGHZ
IDCODE
USERCODE
FA
FC
FE
FD
00FA
00FC
00FE
00FD
Enables boundary-scan CLAMP operation
Places all outputs in high-impedance state
simultaneously
Enables shifting out 32-bit IDCODE
Enables shifting out 32-bit USERCODE
FF
01
00
FFFF
0001
0000
Enables BYPASS
Enables boundary-scan SAMPLE/PRELOAD operation
Enables boundary-scan EXTEST operation
XCFxxS IR[7:0]
(hex)
XCFxxP IR[15:0]
(hex)
Instruction Description
Platform Flash PROM
Specific Instructions
Initiates FPGA configuration by pulsing CF pin Low
once. (For the XCFxxP this command also resets the
selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision
selection bits.)
(1)
CONFIG
EE
00EE
Notes:
1.
For more information see
Table 7:
XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
TDI
→
IR[7:5]
Reserved
IR[4]
ISC Status
IR[3]
Security
IR[2]
0
IR[1:0]
01
→
TDO
Table 8:
XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
IR[15:9]
TDI
→
Reserved
IR[8:7]
ISC Error
IR[6:5]
ER/PROG
Error
IR[4]
ER/PROG
Status
IR[3]
ISC Status
IR[2]
DONE
IR[1:0]
01
→
TDO
DS123 (v2.9) May 09, 2006
6
XILINX [ XILINX, INC ]
