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Platform Flash In-System Programmable Configuration PROMS
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A single 32-Mbit PROM contains four 8-Mbit memory
blocks, and can therefore store up to four separate
design revisions: one 32-Mbit design revision, two
16-Mbit design revisions, three 8-Mbit design revisions,
four 8-Mbit design revisions, and so on.
Because of the 8-Mbit minimum size requirement for
each revision, a single 16-Mbit PROM can only store
up to two separate design revisions: one 16-Mbit
design revision, one 8-Mbit design revision, or two
8-Mbit design revisions.
A single 8-Mbit PROM can store only one 8-Mbit
design revision.
When the FPGA deasserts BUSY, indicating that it is ready
to receive additional configuration data, the PROM will
begin driving new data onto the configuration interface.
Decompression
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include a
built-in data decompressor compatible with Xilinx advanced
compression technology. Compressed Platform Flash
PROM files are created from the target FPGA bitstream(s)
using the iMPACT software. Only Slave Serial and Slave
SelectMAP (parallel) configuration modes are supported for
FPGA configuration when using a XCFxxP PROM
programmed with a compressed bitstream. Compression
rates will vary depending on several factors, including the
target device family and the target design contents.
The decompression option is enabled during the PROM
programming sequence. The PROM decompresses the
stored data before driving both clock and data onto the
FPGA's configuration interface. If Decompression is
enabled, then the Platform Flash clock output pin
(CLKOUT) must be used as the clock signal for the
configuration interface, driving the target FPGA's
configuration clock input pin (CCLK). Either the PROM's
CLK input pin or the internal oscillator must be selected as
the source for CLKOUT. Any target FPGA connected to the
PROM must operate as slave in the configuration chain,
with the configuration mode set to Slave Serial mode or
Slave SelectMap (parallel) mode.
When decompression is enabled, the CLKOUT signal
becomes a controlled clock output with a reduced maximum
frequency. When decompressed data is not ready, the
CLKOUT pin is put into a high-Z state and must be pulled
High externally to provide a known state.
The BUSY input is automatically disabled when
decompression is enabled.
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Larger design revisions can be split over several cascaded
PROMs. For example, two 32-Mbit PROMs can store up to
four separate design revisions: one 64-Mbit design revision,
two 32-Mbit design revisions, three 16-Mbit design revisions,
four 16-Mbit design revisions, and so on. When cascading
one 16-Mbit PROM and one 8-Mbit PROM, there are 24 Mbits
of available space, and therefore up to three separate design
revisions can be stored: one 24-Mbit design revision, two
8-Mbit design revisions, or three 8-Mbit design revisions.
See
for a few basic examples of how
multiple revisions can be stored. The design revision
partitioning is handled automatically during file generation
in iMPACT.
During the PROM file creation, each design revision is
assigned a revision number:
Revision 0 = '00'
Revision 1 = '01'
Revision 2 = '10'
Revision 3 = '11'
After programming the Platform Flash PROM with a set of
design revisions, a particular design revision can be
selected using the external REV_SEL[1:0] pins or using the
internal programmable design revision control bits. The
EN_EXT_SEL pin determines if the external pins or internal
bits are used to select the design revision. When
EN_EXT_SEL is Low, design revision selection is controlled
by the external Revision Select pins, REV_SEL[1:0]. When
EN_EXT_SEL is High, design revision selection is
controlled by the internal programmable Revision Select
control bits. During power up, the design revision selection
inputs (pins or control bits) are sampled internally. After
power up, the design revision selection inputs are sampled
again when any of the following events occur:
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On the rising edge of CE
On the falling edge of OE/RESET (when CE is Low)
On the rising edge of CF (when CE is Low)
When reconfiguration is initiated by using the JTAG
CONFIG instruction.
Design Revisioning
Design Revisioning allows the user to create up to four
unique design revisions on a single PROM or stored across
multiple cascaded PROMs. Design Revisioning is supported
for the 8/16/32 Mbit XCFxxP Platform Flash PROMs in both
serial and parallel modes. Design Revisioning can be used
with compressed PROM files, and also when the CLKOUT
feature is enabled. The PROM programming files along with
the revision information files (.cfi) are created using the
iMPACT software. The
.cfi
file is required to enable design
revision programming in iMPACT.
A single design revision is composed of from 1 to
n
8-Mbit
memory blocks. If a single design revision contains less
than 8 Mbits of data, then the remaining space is padded
with all ones. A larger design revision can span several
8-Mbit memory blocks, and any space remaining in the last
8-Mbit memory block is padded with all ones.
The data from the selected design revision is then
presented on the FPGA configuration interface.
DS123 (v2.9) May 09, 2006
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XILINX [ XILINX, INC ]
