Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 52: OSERDES Switching Characteristics
Speed Grade
Symbol Description
Units
-3
-2
-1 (XC) -1 (XQ)
-1L
Setup/Hold
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
OCE input Setup/Hold with respect to CLK
0.23/
–0.10
0.28/
–0.10
0.31/
–0.10
0.35/
–0.10
0.36/
–0.15
ns
ns
ns
ns
ns
ns
(1)
TOSDCK_T/TOSCKD_T
0.44/
–0.10
0.51/
–0.09
0.56/
–0.08
0.60/
–0.08
0.68/
–0.15
(1)
T
OSDCK_T2/TOSCKD_T2
TOSCCK_OCE/TOSCKC_OCE
TOSCCK_S
OSCCK_TCE/TOSCKC_TCE
0.25/
–0.10
0.27/
–0.09
0.31/
–0.08
0.31/
–0.08
0.47/
–0.15
0.17/
–0.03
0.20/
–0.03
0.22/
–0.03
0.27/
–0.03
0.27/
–0.04
SR (Reset) input Setup with respect to
CLKDIV
0.07
0.07
0.07
0.07
0.08
T
TCE input Setup/Hold with respect to CLK
0.15/
–0.04
0.19/
–0.04
0.21/
–0.04
0.27/
–0.04
0.29/
–0.05
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
Clock to out from CLK to TQ
0.63
0.63
0.71
0.71
0.82
0.82
0.82
0.82
0.93
0.93
ns
ns
TOSCKO_TQ
Combinatorial
TOSDO_TTQ
T input to TQ Out
0.76
0.84
0.97
0.97
1.11
ns
Notes:
1.
T
and T
are reported as T
/T
in TRACE report.
OSDCK_T2
OSCKD_T2
OSDCK_T OSCKD_T
DS152 (v3.6) March 18, 2014
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Product Specification
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