Spartan-6 Family Overview
Spartan-6 FPGA Ordering Information
The Spartan-6 FPGA ordering information shown in
applies to all packages, including Pb-Free.
X-Ref Target - Figure 1
Example: XC6SLX100T-2FGG676C
Device Type
Speed Grade
(-L1
(1)
, -2, -3, -4
(2)
)
Note:
1) -L1 is the ordering code for the lower power
version.
Not
all devices are offered in this
version
(LX only).
See the Spartan-6 FPGA data sheet for more information.
2) -4 speed grades are not available in all devices (LXT only).
Temperature Range:
C = Commercial (T
j
= 0°C to +85°C)
I = Industrial (T
j
= –40°C to +100°C)
Number
of Pins
Pb-Free
Package Type
DS160_01_022410
Figure 1:
Spartan-6 FPGA Ordering Information
Revision History
The following table shows the revision history for this document:
Date
02/02/09
05/05/09
Version
1.0
1.1
Initial Xilinx release.
Description of Revisions
Updated and simplified
and
sections on
Clarified PCI support on
only for the 33 MHz specification. Revised number of logic cells, slices, and maximum user I/O, and
added number of flip-flops to
In
revised user I/O counts, removed the XC6SLX25 in
the CSG225 package and the XC6SLX45T in the FGG676 package, added XC6SLX9 in the FT(G)256
package and XC6SLX45 in the CSG324 package, and added notes. Clerical edits to the following
sections:
and
Clarified I/O pin range, V
REF
banks,
and electrical characteristics in the
section.
Updated device/package combinations in
and
including adding the XC6SLX75 and
XC6SLX75T devices. Added ordering information and FPGA documentation sections. Removed
partial reconfiguration discussion from the
section.
Updated
to show -4 speed grade. Added 64-bit PCI support on
Updated User
I/O numbers in
Clarifying edits to these sections:
and PCI Express documentation.
Updated the slice counts for the LX25 and LX25T in
Revised the
section. Added to the
section. Changed the PLL VCO maximum
frequency to 1080 MHz and the DSP48A1 slice maximum frequency to 320 MHz due to the addition
of the -4 speed specification. Clarified configurations in the
section.
Updated
operating rate.
06/24/09
1.2
11/05/09
1.3
03/03/10
1.4
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT
THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS160 (v1.4) March 3, 2010
Advance Product Specification
9
XILINX [ XILINX, INC ]
