Spartan-6 Family Overview
Spartan-6 FPGA Feature Summary
Table 1: Spartan-6 FPGA Feature Summary by Device
Configurable Logic Blocks (CLBs)
Block RAM Blocks
(4)
Memory
Controller
Blocks
Endpoint
Maximum
GTP
Total Max
I/O User
Logic
DSP48A1
(5)
Device
Max
Flip-Flops Distributed
RAM (Kb)
CMTs
Blocks for
(1)
(3)
Cells
Slices
(2)
Slices
18 Kb
Max (Kb)
PCI Express Transceivers Banks I/O
(Max)
XC6SLX4
3,840
9,152
600
4,800
11,440
18,224
30,064
54,576
93,296
75
90
8
12
32
216
576
2
2
2
2
4
6
6
6
2
4
6
6
6
0
2
2
2
2
4
4
4
2
2
4
4
4
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
2
4
8
8
8
4
4
4
4
4
6
6
6
4
4
6
6
6
132
200
232
266
358
408
480
576
250
296
348
498
540
XC6SLX9
1,430
2,278
3,758
6,822
11,662
16
XC6SLX16
XC6SLX25
XC6SLX45
XC6SLX75
XC6SLX100
XC6SLX150
XC6SLX25T
XC6SLX45T
XC6SLX75T
XC6SLX100T
XC6SLX150T
14,579
24,051
43,661
74,637
136
229
401
692
976
1,355
229
401
692
976
1,355
32
32
576
38
52
936
58
116
172
268
268
52
2,088
3,096
4,824
4,824
936
132
180
180
38
101,261 15,822 126,576
147,443 23,038 184,304
24,051
43,661
74,637
3,758
6,822
30,064
54,576
93,296
58
116
172
268
268
2,088
3,096
4,824
4,824
11,662
132
180
180
101,261 15,822 126,576
147,443 23,038 184,304
Notes:
1. Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture.
2. Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops.
3. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator.
4. Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.
5. Each CMT contains two DCMs and one PLL.
DS160 (v1.4) March 3, 2010
www.xilinx.com
Advance Product Specification
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XILINX [ XILINX, INC ]
