R
XC4000XLA/XV Field Programmable Gate Arrays
JTAG Enhancements
XC4000XLA/XV devices have improved JTAG functionality
and performance in the following areas:
•
IDCODE
- The IDCODE register in JTAG is now
supported. All future Xilinx FPGAs will support the
IDCODE register. By using the IDCODE, the device
connected to the JTAG port can be determined. The
use of the IDCODE enables selective configuration
dependent upon the FPGA found. The IDCODE register
has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
Where:
c = the company code;
a = the array dimension in CLBs;
f = the Family code;
v = the die version number
Family Codes = 01 for XLA;
= 02 for SpartanXL;
= 03 for Virtex;
= 07 for XV.
Xilinx company code = 49 (hex)
Table 4: IDCODEs assigned to XC4000XLA/XV FPGAs
FPGA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
IDCODE
0x00218093
0x0021c093
0x00220093
0x00224093
0x00228093
0x0022c093
0x00230093
0x00238093
0x00e40093
0x00e48093
0x00e54093
0x00e5c093
•
Bypass FF -
Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop
and during EXTEST or SAMPLE/PRELOAD for the IOB
register.
XV and XLA Family Differences
The high density of the XC4000XV family FPGAs is
achieved by using advanced 0.25 micron silicon technol-
ogy. A 2.5 Volt power supply (VCCINT) is necessary to pro-
vide the reduced supply voltage required by 0.25 micron
internal logic, however to maintain TTL compatibility a 3.3V
power supply (VCCIO) is required by the I/O.
To accommodate the higher gate capacity of XV devices,
additional interconnect has been added. These differences
are detailed below.
•
VCCINT (2.5 Volt) Power Supply Pins
The XV family of FPGAs requires a 2.5V power supply
for internal logic, which is named VCCINT. The pins
assigned to the VCCINT supply are named in the pinout
guide for the XC4000XV FPGAs and in
•
VCCIO (3.3 Volt) Power Supply Pins
Both the XV and XLA FPGAs use a 3.3V power supply
to power the I/O pins. The I/O supply is named VCCIO
in the XV family.
•
Octal-Length Interconnect Channels
The XC40110XV, XC40150XV, XC40200XV, and
XC40250XV have enhanced routing. Eight routing
channels of octal length have been added to each CLB
in both vertical and horizontal dimensions.
6
XLA-to-XL Socket Compatibility
The XC4000XLA devices are generally available in the
same packages as equivalent XL devices, however the
range of packages available for the XC4085XLA has been
extended to include smaller packages such as the HQ240.
XV-to-XL/XLA Socket Compatibility
XC4000XV devices are available in five package options,
pin-grid PG599 and ball-grid BG560, BG432, and BG352
and quad-flatpack HQ240. With the exception of the
VCCINT power pins, XC4000XV FPGAs are compatible
with XL and XLA devices in these packages if the following
guidelines are followed:
• Lay out the PCB for the XV pinout.
• When an XL or XLA device is installed disconnect the
VCCINT (2.5 V) supply. For the PG599, VCCINT should
be connected to 3.3V. For BG560, BG432 and BG352
and HQ240 packages, the VCCINT voltage source
should be left unconnected. The unused I/O pins in the
XL/XLA devices connected to VCCINT will be pulled up
to 3.3V. Care must be taken to insure that these pins
are not driven when the XL/XLA device is operative.
• When an XC4000XV is installed, the VCCINT pins must
•
Configuration State
- The configuration state is
available to JTAG controllers.
•
Configure Disable
- The JTAG port can be prevented
from reconfiguring the FPGA
•
TCK Startup
- TCK can now be used to clock the
start-up block in addition to other user clocks.
•
CCLK holdoff
- Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the
release of INIT pin and CCLK cycling.
•
Reissue configure
- The Boundary Scan Configure
can be reissued to recover from an unfinished attempt
to configure the device.
DS015 (v1.3) October 18, 1999 - Product Specification
6-161
XILINX [ XILINX, INC ]
