R
XC4000XLA/XV Field Programmable Gate Arrays
The XV devices also incorporate additional routing
resources in the form of 8 octal-length segmented routing
channels vertically and horizontally per row and column.
General Description
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of fifteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, increased speed, abundant
routing resources, and new, sophisticated software to
achieve fully automated implementation of complex,
high-density, high-performance designs.
XLA/XV and XL Family Differences
The XC4000XLA/XV families of FPGAs are logically identi-
cal to XC4000EX and XC4000XL FPGAs, however I/O,
configuration logic, JTAG functionality, and performance
have been enhanced. In addition, they deliver:
•
Improved Performance
XLA/XV devices benefit from advance processing
technology and a reduction in interconnect capacitance
which improves performance over XL devices by more
than 30%.
•
Lower Power
XLA/XV devices have reduced power requirements
compared to equivalent XL devices.
•
Shorter routing delays
The smaller die of XLA/XV devices directly reduces
clock delays and the delay of high-fanout signals. The
reduction in clock delay allows improved pin-to-pin I/O
specifications.
•
Lower Cost
XLA/XV device cost is directly related to the die size
and has been reduced significantly from that of
equivalent XL devices.
•
Express mode configuration
Express mode configuration is available on the XLA and
XV devices.
Figure 1: Cross Section of Xilinx 0.25 micron, 5 layer
metal XC4000XV FPGA.
Visible features are five layers of
metallization, tungsten plug vias and trench isolation. The
small gaps above the lowest layer are 0.25 micron
polysilicon MOSFET gates. The excellent planarity of each
metal layer is due to the use of “chemical-mechanical
polishing” or CMP. In effect, each layer is ground flat before
a new layer is added.
IOB Enhancements
•
12/24 mA Output Drive
The XLA/XV family of FPGAs allow individual IOBs to
be configured as high drive outputs. Each output can be
configured to have 24 mA drive strength as opposed to
the standard default strength of 12 mA.
•
VCC Clamping Diode
XLA and XV FPGAs have an optional clamping diode
connected from each output to VCC (VCCIO for XV).
When enabled they clamp ringing transients back to the
3.3V supply rail. This clamping action is required in
3.3V PCI applications. VCC clamping is a global option
affecting all I/O pins. If enabled, TTL I/O compatibility is
maintained, but full 5.0 Volt I/O tolerance is sacrificed.
•
Enhanced ESD protection
An improved ESD structure allows XV devices to safely
pass the stringent 5V PCI (4.2.1.3) ringing test. This
test applies an 11V pulse to each IOB for 11 ns via a 55
ohm resistor.
•
Full 3.3V and 5.0V PCI compliance
The addition of 12/24 mA drive, optional 3.3V clamping
and improved ESD provides full compliance with either
3.3V or 5.0V PCI specifications.
Technology Advantage
XC4000XLA/XV FPGAs use 5 layer metal silicon technol-
ogy to improve performance while reducing device cost and
power. In addition, IOB enhancements provide full PCI
compliance and the JTAG functionality is expanded.
Low Power Internal Logic
XC4000XV FPGAs incorporate all the features of the XLA
devices but require a separate 2.5V power supply for inter-
nal logic. I/O pads are still driven from a 3.3V power supply.
The 2.5V logic supply is named VCCINT and the 3.3 V IO
supply is named VCCIO.
6-158
DS015 (v1.3) October 18, 1999 - Product Specification
XILINX [ XILINX, INC ]
