R
XC4000XLA/XV Field Programmable Gate Arrays
•
BUFGE (I,O)
- The Global Early Buffer
•
BUFGLS (I,O)-
The Global Low Skew Buffer
•
BUFFCLK (I,O)
- The FastCLK Buffer
•
ILFFX (D, GF, CE, C, Q)
- The Fast Capture Latch
Macro
Locating I/O elements
- It is necessary to connect these
elements to a particular I/O pad in order to select which
buffer or fast capture latch will be used.
Restricted Clock Loading
- Because the input hold
requirement is a function of internal clock delay, it may be
necessary to restrict the routing of BUFGE to IOBs along
the top and bottom of the die to obtain sub-ns clock delays.
BUFGE 1
BUFGE 6
Using Fast I/O CLKS
There are several issues associated with implementing fast
I/O clocks by using multiple FastCLK and BUFGE clock
buffers for I/O transfers and a BUFGLS clock buffer for
internal logic.
Reduced Clock to Out Period
- When transferring data
from a BUFGLS clocked register to an IOB output register
which is clocked with a fast I/O clock, the total amount of
time available for the transfer is reduced.
Using Fast Capture Latch in IOB input -
It is necessary to
transfer data captured with the fast I/O clock edge to a
delayed BUFGLS clock without error. The use of the Fast
Capture Latch in the IOBs provides this functionality.
Driving multiple clock inputs
- Since each FastCLK input
can only reach one octant of IOBs it will usually be neces-
sary to drive multiple FastCLK and BUFGE input pads with
a copy of the system clock. Xilinx recommends that sys-
tems which use multiple FastCLK and BUFGE input buffers
use a “Zero Delay” clock buffer such as the Cypress
CY2308 to drive up to 8 input pins. These devices contain a
Phase locked loop to eliminate clock delay, and specify less
than 250ps output jitter.
PCB layout
- The recommended layout is to place the PLL
underneath the FPGA on the reverse side of the PCB. All 8
clock lines should be of equal length. This arrangement will
allow all the clock line to be less than 2 cm in length which
will generally eliminate the need for clock termination.
Advancing the FPGAs clock -
An additional advantage to
using a PLL-equipped clock buffer is that it can advance the
FPGA clocks relative to the system clock by incorporating
additional board delay in the feedback path. Approximately
6 inches of trace length are necessary to delay the signal
by 1 ns.
Advancing the FPGA’s clock directly reduces input hold
requirements and improves clock to out delay. FPGA clocks
should not be advanced more than the guaranteed mini-
mum Output Hold Time (minus any associated clock jitter)
or the outputs may change state before the system clock
edge. For XLA and XV FPGAs the Output Hold Time is
specified as a minimum Clock to Output Delay in the tables
in the respective family Electrical Specification sections.
The maximum recommended clock advance equals this
value minus any clock jitter.
Instantiating I/O elements-
Depending on the design
environment, it may be necessary to instantiate the fast I/O
elements. They are found in the libraries as:
FCLK 1
FCLK 4
FCLK 2
BUFGLS 2
BUFGE 2
FCLK 3
BUFGE 5
Figure 2: Location of FastCLK, BUFGE and BUFGLS
Clock Buffers in XC4000XLA/XV FPGAs
SysClk
PLL
Clock
O0
Buffer
O1
O2
O3
O4
O5
FB
O6
Ref
O7
BUFGE
1
BUFGE
2
BUFGE
5
BUFGE
6
FCLK1
FCLK2
FCLK3
FCLK4
XC4000XLA
XC4000XV
Figure 3: Diagram of XC4000XLA/XV FPGA
Connected to PLL Clock Buffer Driving 4 BUFGE and
4 FastCLK Clock Buffers.
6-160
DS015 (v1.3) October 18, 1999 - Product Specification
XILINX [ XILINX, INC ]
