XC4000E Logic Cell Array Family
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
C inputs via H’ to X/Y outputs
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1,F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators.
Sequential Delays
Clock K to outputs Q
Set-up Time before Clock K
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
C
IN
input via F'/G'
C
IN
input via F'/G' and H'
Hold Time after Clock K
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
Symbol
Min
-4
Max
-3
Min Max
-2
Min Max Units
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
T
CKO
T
ICK
T
IHCK
T
HHCK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
T
CKI
T
CKIH
T
CKHH
T
CKDI
T
CKEC
T
CKR
T
CH
T
CL
T
RPW
T
RIO
T
MRW
T
MRQ
ADVANCE INFORMATION
T
ILO
T
IHO
T
HHO
2.0
3.6
2.9
ns
ns
ns
2.6
4.4
1.7
3.3
0.7
ns
ns
ns
ns
ns
2.4
ns
2.3
4.0
3.3
1.9
2.6
1.7
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
4.0
4.0
ns
ns
4.0
4.0
ns
ns
18.9
14.4
ns
ns
* Timing is based on the XC4005E. For other devices see XACT timing calculator.
4
XILINX [ XILINX, INC ]
