XC4000E Logic Cell Array Family
XC4000E compared to XC4000
IOB Clock Enable
AnyXC4000Edeviceisa100%compatiblesupersetofthe
equivalent XC4000 device, not only functionally, but also
electrically, and in pin-out and configuration bitstream.
Thetwoflip-flopsineachIOBhaveacommonclockenable
input,which through configuration can be activated indi-
vidually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This makes the IOBs more versatile, and avoids the
need for clock gating.
The XC4000E devices have the following additional func-
tions, most of which are invoked through options in the
configuration bitstream:
Output Drivers
Synchronous RAM
The output pull-up structure can be globally configured to
be either a TTL-like totem-pole (n-channel pull-up transis-
tor, pulling to a voltage one threshold below Vcc, just like
XC4000) or to be CMOS (p-channel pull-up transistor
pulling to Vcc). Also, the configurable pull-up resistor in
XC4000E is a p-channel transistor that pulls to Vcc,
whereas in XC4000 it is an n-channel transistor that pulls
to a voltage one threshold below Vcc.
ThetwoRAMsinanyCLBcanbechangedtosynchronous
write operation. In this synchronous mode, the internal
write operation is controlled by the same clock that drives
the flip-flops. The clock polarity is programmable for the
RAM (both F and G function generators together), but is
independent of the chosen flip-flop polarity. Address,
Data, and WE inputs are latched by this rising or falling
clock edge, and a short internal write pulse is generated
right after the clock edge. This self-timed write operation is
thus effectively edge-triggered.
Input Thresholds
The input thresholds can be globally configured for either
TTL ( 1.2 V threshold) or CMOS ( 2.5 V threshold ), just like
XC2000 and XC3000 inputs. Note that the two global
adjustments of input threshold and output level are inde-
pendent of each other.
The read operation is not affected by this change to a
synchronous write.
Dual-Port RAM
A separate option converts the 16 x 2 RAM in any CLB into
a 16 x 1 dual-port RAM. In this mode, any operation that
writesintotheF-RAM, automaticallyalsowritesintotheG-
RAM, using the F address. The G-address can, therefore,
not be used to write into the G-RAM.
Global Signal Access to Logic
There is additional access from global clocks to the F and
G function generator inputs.
Mode-Pin Pull-Up Resistors
During configuration, the three mode pins, M0, M1, and
M2, have weak pull-up resistors. For the most popular
configuration mode, Slave Serial, the mode pins can thus
be left unconnected.
The CLB can thus be used as an asymmetrical dual-port
RAM, withFbeingthereadaddressfortheF-RAMandthe
write address for both F- and G-RAM, while G is the read
address for the G-RAM. Note that F and G can still be
independent read addresses, as they are in XC4000. The
two RAMs together have one read/write port using the F
address, and one read-only port using the G address.
For user mode, the three mode inputs can individually be
configured with or without weak pull-up or pull-down
resistors
The PROGRAM input pin has a permanent weak pull-up.
Each CLB can be configured as function generators either
asynchronous single-port, synchronous single-port, or
synchronous dual-port.
Soft Startup
Like XC3000A, the XC4000E family has “Soft Startup”.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This avoids the potential
ground bounce when all outputs are turned on simulta-
neously. After start-up, the slew rate of the individual
outputs is, as in the XC4000 family, determined by the
individual configuration option.
H-Function Generator
In XC4000E, the H function generator is more versatile. Its
inputs can come not only from the F and G function
generators but also from up to three control input lines.
The H function generator can be totally or partially inde-
pendent of the other two function generators.
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