Spartan-3E FPGA Family: Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3E FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination.
Spartan-3E FPGAs support the following single-ended
standards:
•
•
3.3V low-voltage TTL (LVTTL)
•
•
Master Serial from a Xilinx Platform Flash PROM
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
•
•
3V PCI at 33 MHz, and in some devices, 66 MHz
•
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
HSTL I and III at 1.8V, commonly used in memory
applications
•
•
•
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
•
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
Spartan-3E FPGAs support the following differential
standards:
Furthermore, Spartan-3E FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single parallel NOR Flash. The
FPGA application controls which configuration to load next
and when to load it.
•
•
•
•
•
•
•
LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
VQ100
VQG100
CP132
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
Package
Footprint
Size (mm)
16 x 16
8 x 8
22 x 22
30.5 x 30.5
17 x 17
19 x 19
21 x 21
23 x 23
Device
User
Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff
66(2)
30
83
35
108
40
XC3S100E
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9(7)
(2)
(11)
(2)
(28)
(4)
66
(7)
30
(2)
92
(7)
41
(2)
108
(28)
40
(4)
158
(32)
65
(5)
172
(40)
68
(8)
XC3S250E
XC3S500E
XC3S1200E
66(3)
(7)
30
(2)
92
(7)
41
(2)
158
(32)
65
(5)
190
(41)
77
(8)
232
(56)
92
(12)
-
-
-
-
-
-
190
(40)
77
(8)
250
(56)
99
(12)
304
(72)
124
(20)
-
-
-
-
-
-
-
-
-
-
-
-
250
(56)
99
(12)
304
(72)
124
(20)
376 156
(82) (21)
XC3S1600E
Notes:
-
-
1. All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4, Pinout Descriptions.
2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
3. The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical
and general references to the VQ100 will apply to the XC3S500E.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
4
XILINX [ XILINX, INC ]
