8
Spartan-3E FPGA Family:
Introduction and Ordering Information
DS312 (v4.2) December 14, 2018
Product Specification
Introduction
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LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
622+ Mb/s data transfer rate per I/O
True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL
differential I/O
Enhanced Double Data Rate (DDR) support
DDR SDRAM support up to 333 Mb/s
The Spartan®-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic
applications. The five-member family offers densities
ranging from 100,000 to 1.6 million system gates, as shown
in Table 1.
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The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of
configuration. These Spartan-3E FPGA enhancements,
combined with advanced 90 nm process technology, deliver
more functionality and bandwidth per dollar than was
previously possible, setting new standards in the
programmable logic industry.
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Abundant, flexible logic resources
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Densities up to 33,192 logic cells, including optional shift
register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
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Hierarchical SelectRAM™ memory architecture
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Up to 648 Kbits of fast block RAM
Up to 231 Kbits of efficient distributed RAM
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home
networking, display/projection, and digital television
equipment.
Up to eight Digital Clock Managers (DCMs)
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Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 300 MHz)
The Spartan-3E family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
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Eight global clocks plus eight additional clocks per each half
of device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
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Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Low-cost Xilinx® Platform Flash with JTAG
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Complete Xilinx ISE® and WebPACK™ software
MicroBlaze™ and PicoBlaze embedded processor cores
Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in
some devices)
Low-cost QFP and BGA packaging options
Common footprints support easy density migration
Pb-free packaging options
Features
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Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
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Proven advanced 90-nanometer process technology
Multi-voltage, multi-standard SelectIO™ interface pins
XA Automotive version available
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Up to 376 I/O pins or 156 differential signal pairs
Table 1: Summary of Spartan-3E FPGA Attributes
CLB Array
Block
RAM
Maximum
Differential
I/O Pairs
(One CLB = Four Slices)
System Equivalent
Gates Logic Cells
Distributed
RAM bits(1)
Dedicated
Multipliers
Maximum
User I/O
Device
DCMs
Total
CLBs
Total
Slices
bits(1)
Rows Columns
XC3S100E
XC3S250E
XC3S500E
XC3S1200E 1200K
XC3S1600E 1600K
Notes:
100K
250K
500K
2,160
5,508
10,476
19,512
33,192
22
34
46
60
76
16
26
34
46
58
240
612
1,164
2,168
3,688
960
15K
38K
73K
136K
231K
72K
4
2
4
4
8
8
108
172
232
304
376
40
68
92
124
156
2,448
4,656
8,672
14,752
216K
360K
504K
648K
12
20
28
36
1. By convention, one Kb is equivalent to 1,024 bits.
© Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
2
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