R
Functional Description
+1.2V
+3.3V
Atmel
AT45DB
VCCINT
DataFlash
P
P
HSWAP
VCCO_0
VCCO_0
+3.3V
I
VCC
VCCO_2
MOSI
SI
Power-on monitor is only required if
SPI Mode
DIN
SO
CS
WP
+3.3V (VCCO_2) supply is last supply
in power-on sequence, after VCCINT
and VCCAUX. Must delay FPGA
configuration for > 20 ms after SPI
DataFlash reaches its minimum VCC.
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
W
‘1’
RESET
RDY/BUSY
SCK
Force FPGA INIT_B input or
PROG_B
input Low with an open-drain or open-
collector driver.
Variant Select
Spartan-3E
FPGA
‘1’
‘1’
‘0’
VS2
VS1
VS0
GND
+3.3V
+3.3V
CCLK
DOUT
INIT_B
Power-On
Monitor
INIT_B
+2.5V
JTAG
TDI
+2.5V
VCCAUX
TDO
+2.5V
TDI
TMS
TCK
TDO
TMS
TCK
or
PROG_B
DONE
+3.3V
GND
Power-On
Monitor
PROG_B
PROG_B
Recommend
open-drain
driver
DS312-2_50a_022305
Figure 51: Atmel SPI-based DataFlash Configuration Interface
64
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
