欢迎访问ic37.com |
会员登录 免费注册
发布采购

XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第1页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第2页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第4页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第5页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第6页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第7页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第8页浏览型号XC3S1600E-4FGG320C的Datasheet PDF文件第9页  
R
Introduction and Ordering Information  
Architectural Overview  
The Spartan-3E family architecture consists of five funda-  
mental programmable functional elements:  
Digital Clock Manager (DCM) Blocks provide  
self-calibrating, fully digital solutions for distributing,  
delaying, multiplying, dividing, and phase-shifting clock  
signals.  
Configurable Logic Blocks (CLBs) contain flexible  
Look-Up Tables (LUTs) that implement logic plus  
storage elements used as flip-flops or latches. CLBs  
perform a wide variety of logical functions as well as  
store data.  
These elements are organized as shown in Figure 1. A ring  
of IOBs surrounds a regular array of CLBs. Each device has  
two columns of block RAM except for the XC3S100E, which  
has one column. Each RAM column consists of several  
18-Kbit RAM blocks. Each block RAM is associated with a  
dedicated multiplier. The DCMs are positioned in the center  
with two at the top and two at the bottom of the device. The  
XC3S100E has only one DCM at the top and bottom, while  
the XC3S1200E and XC3S1600E add two DCMs in the  
middle of the left and right sides.  
Input/Output Blocks (IOBs) control the flow of data  
between the I/O pins and the internal logic of the  
device. Each IOB supports bidirectional data flow plus  
3-state operation. Supports a variety of signal  
standards, including four high-performance differential  
standards. Double Data-Rate (DDR) registers are  
included.  
Block RAM provides data storage in the form of  
18-Kbit dual-port blocks.  
The Spartan-3E family features a rich network of traces that  
interconnect all five functional elements, transmitting sig-  
nals among them. Each functional element has an associ-  
ated switch matrix that permits multiple connections to the  
routing.  
Multiplier Blocks accept two 18-bit binary numbers as  
inputs and calculate the product.  
Notes:  
1. The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as  
indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom.  
Figure 1: Spartan-3E Family Architecture  
2
www.xilinx.com  
DS312-1 (v1.1) March 21, 2005  
Advance Product Specification  
 复制成功!