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Spartan-3E FPGA Family:
Introduction and Ordering
Information
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DS312-1 (v1.1) March 21, 2005
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Advance Product Specification
Introduction
The Spartan™-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic applica-
tions. The five-member family offers densities ranging from
100,000 to 1.6 million system gates, as shown in
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of config-
uration. These Spartan-3E enhancements, combined with
advanced 90 nm process technology, deliver more function-
ality and bandwidth per dollar than was previously possible,
setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection, and digital television equipment.
The Spartan-3E family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
- True LVDS, RSDS, mini-LVDS differential I/O
- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
- Enhanced Double Data Rate (DDR) support
Abundant, flexible logic resources
- Densities up to 33,192 logic cells, including
optional shift register or distributed RAM support
- Efficient wide multiplexers, wide logic
- Fast look-ahead carry logic
- Enhanced 18 x 18 multipliers with optional pipeline
- IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
- Up to 648 Kbits of fast block RAM
- Up to 231 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
- Clock skew elimination (delay locked loop)
- Frequency synthesis, multiplication, division
- High-resolution phase shifting
- Wide frequency range (5 MHz to over 300 MHz)
Eight global clocks and eight clocks for each half of
device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
- Low-cost, space-saving SPI serial Flash PROM
- x8 or x8/x16 parallel NOR Flash PROM
- Low-cost Xilinx Platform Flash with JTAG
Complete Xilinx ISE™, WebPACK™ development
system support
MicroBlaze™, PicoBlaze™ embedded processor cores
Fully compliant 32-/64-bit 33/66 MHz PCI support
Low-cost QFP and BGA packaging options
- Common footprints support easy density migration
- Pb-free packaging options
•
•
•
•
•
Features
•
•
•
Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
Proven advanced 90-nanometer process technology
Multi-voltage, multi-standard SelectIO™ interface pins
- Up to 376 I/O pins or 156 differential signal pairs
- LVCMOS, LVTTL, HSTL, and SSTL single-ended
signal standards
•
•
•
•
Table 1:
Summary of Spartan-3E FPGA Attributes
Equivalent
Logic
Cells
2,160
5,508
10,476
19,512
33,192
CLB Array
(One CLB = Four Slices)
Rows Columns
22
34
46
60
76
16
26
34
46
58
Total
CLBs
240
612
1,164
2,168
3,688
Total
Slices
960
2,448
4,656
8,672
14,752
Distributed
RAM bits
15K
38K
73K
136K
231K
Block
RAM
bits
72K
216K
360K
504K
648K
Maximum
Differential
I/O Pairs
40
68
92
124
156
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
System
Gates
100K
250K
500K
1200K
1600K
Dedicated
Multipliers DCMs
4
12
20
28
36
2
4
4
8
8
Maximum
User I/O
108
172
232
304
376
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-1 (v1.1) March 21, 2005
Advance Product Specification
1
XILINX [ XILINX, INC ]
