R
Pinout Descriptions
User I/Os by Bank
Table 25, Table 26, and Table 27 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FG320 package.
Table 25: User I/Os Per Bank for XC3S500E in the FG320 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
29
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
58
58
14
10
13
11
48
6
5
8
0
Right
22
21
24
0
Bottom
Left
58
17
4
0
58
34
5
8
TOTAL
232
102
46
20
16
Table 26: User I/Os Per Bank for XC3S1200E in the FG320 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
34
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
61
63
12
12
11
12
47
6
5
8
0
Right
25
21
24
0
Bottom
Left
63
23
5
0
63
38
5
8
TOTAL
250
120
46
21
16
Table 27: User I/Os Per Bank for XC3S1600E in the FG320 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
33
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
61
63
13
12
11
12
48
6
5
8
0
Right
25
21
24
0
Bottom
Left
63
23
5
0
63
38
5
8
TOTAL
250
119
46
21
16
The XC3S500E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S1200E
and the XC3S1600E. The arrows indicate the direction for
easy migration. A double-ended arrow (ꢁꢂ) indicates that
the two pins have identical functionality. A left-facing arrow
(ꢁ) indicates that the pin on the device on the right uncon-
ditionally migrates to the pin on the device on the left. It may
be possible to migrate the opposite direction depending on
the I/O configuration. For example, an I/O pin (Type = I/O)
Footprint Migration Differences
Table 28 summarizes any footprint and functionality differ-
ences between the XC3S500E, the XC3S1200E, and the
XC3S1600E FPGAs that may affect easy migration
between devices available in the FG320 package. There are
26 such balls. All other pins not listed in Table 28 uncondi-
tionally migrate between Spartan-3E devices available in
the FG320 package.
50
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
