R
Functional Description
Q
Q
Q
Q
D
D
D
D
D1
D1
From
PAD
PAD
From
Fabric
Fabric
ODDROUT1
D2
D2
Q
D
ODDRIN2
OCLK1
OCLK2
OCLK1
OCLK2
OCLK1
OCLK1
OCLK2
D1
OCLK2
D1
d
d+2
d+3
d+4
d+5
d+6
d+7
d+8
d+9
d
d+2
d+4
d+6
d+8
d+10
d+9
D2
d+1
D2
d+1
d+3
d+5
d+7
d+5 d+6
PAD
d+6
d+5
d+7 d+8
d
d+1 d+2 d+3 d+4
d+8
PAD
d+7
d
d+1 d+2 d+3 d+4
DS312-2_23_030105
DS312-2_36_030105
Figure 7: Output DDR Using Spartan-3E Cascade
Figure 6: Output DDR (without Cascade Feature)
Feature
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that sup-
port a wide range of I/O signaling standards (Table 3 and
Table 4). The majority of the I/Os also can be used to form
differential pairs to support any of the differential signaling
standards (Table 4).
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to “Entry Strategies for Xilinx Con-
straints” in the Xilinx Software Manuals and Help.
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. Spe-
cial care must be taken to ensure the input voltages do not
exceed VCCO (see Module 3 for the specifications). For a
particular VCCO voltage, Table 3 and Table 4 list all of the
IOSTANDARDs that can be combined and if the IOSTAN-
DARD is supported as an input only or can be used for both
inputs and outputs.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
7
Advance Product Specification
XILINX [ XILINX, INC ]
