R
Pinout Descriptions
Table 17: PQ208 Package Pinout
Table 17: PQ208 Package Pinout
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
PQ208
Pin
Bank
Type
Bank
Type
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
P207
P157
P155
P7
JTAG
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
P67
P117
P170
VCCINT
VCCINT
VCCINT
JTAG
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
User I/Os by Bank
P44
Table 18 indicates how the 158 available user-I/O pins are
distributed between the four I/O banks on the PQ208 pack-
age.
P66
P92
P111
P149
P166
P195
P13
Footprint Migration Differences
The XC3S250E and XC3S500E FPGAs have identical foot-
prints in the PQ208 package. Designs can migrate between
the XC3S250E and XC3S500E without further consider-
ation.
Table 18: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
18
9
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
38
40
6
7
5
3
8
0
Right
21
24
0
Bottom
Left
40
8
6
2
0
40
23
58
6
3
8
TOTAL
158
25
46
13
16
24
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
