R
Pinout Descriptions
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S250E FPGA maps
to a VREF pin on the XC3S500E and XC3S1200E FPGA. If
the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S250E FPGA. This VREF connection on
the board allows future migration to the larger devices with-
out modifying the printed-circuit board.
FT256: 256-ball Fine-pitch, Thin Ball
Grid Array
The 256-lead fine-pitch, thin ball grid array package, FT256,
supports three different Spartan-3E FPGAs, including the
XC3S250E, the XC3S500E, and the XC3S1200E.
Table 19 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
All other balls have nearly identical functionality on all three
devices. Table 23 summarizes the Spartan-3E footprint
migration differences for the FT256 package.
The highlighted rows indicate pinout differences between
the XC3S250E, the XC3S500E, and the XC3S1200E
FPGAs. The XC3S250E has 18 unconnected balls, indi-
cated as N.C. (No Connection) in Table 19 and with the
black diamond character (ꢃ) in both Table 19 and in
Figure 7.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 19: FT256 Package Pinout
FT256
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
Ball
Type
I/O
0
0
0
0
IO
IO
IO
IP
IO
IO
IO
IP
IO
IO
IO
IO
A7
A12
B4
I/O
I/O
B6
250E: INPUT
500E: INPUT
1200E: I/O
0
IP
IP
IO
B10
250E: INPUT
500E: INPUT
1200E: I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO/VREF_0
IO/VREF_0
IO/VREF_0
D9
A14
B14
A13
B13
E11
D11
B11
C11
E10
D10
F9
VREF
I/O
IO_L01N_0
IO_L01N_0
IO_L01N_0
IO_L01P_0
IO_L01P_0
IO_L01P_0
I/O
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L04N_0
IO_L04N_0
IO_L04N_0
I/O
IO_L04P_0
IO_L04P_0
IO_L04P_0
I/O
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L05N_0/VREF_0
IO_L05P_0
VREF
I/O
IO_L06N_0
IO_L06N_0
IO_L06N_0
I/O
IO_L06P_0
IO_L06P_0
IO_L06P_0
I/O
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
IO_L08N_0/GCLK5
IO_L08P_0/GCLK4
IO_L09N_0/GCLK7
GCLK
GCLK
GCLK
E9
A9
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
27
Advance Product Specification
XILINX [ XILINX, INC ]
