R
Spartan-3 FPGA Family: Functional Description
output voltage swing for all standards except GTL and
GTLP.
Table 4: Single-Ended I/O Standards (Values in Volts)
VCCO
Board
All single-ended standards except the LVCMOS, LVTTL,
and PCI varieties require a Reference Voltage (VREF) to
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use such a signal standard, a few specifically
reserved I/O pins on the same bank automatically convert
to VREF inputs. When using one of the LVCMOS standards,
these pins remain I/Os because the VCCO voltage biases
Signal
Standard
For
For
VREF for
Termination
Outputs Inputs Inputs(1) Voltage(VTT
)
SSTL2_I
SSTL2_II
Notes:
2.5
2.5
-
-
1.25
1.25
1.25
1.25
1. Banks 4 and 5 of any Spartan-3 device in a VQ100 package
do not support signal standards using VREF
.
2. The VCCO level used for the GTL and GTLP standards must
be no lower than the termination voltage (VTT), nor can it be
lower than the voltage at the I/O pad.
the input-switching threshold, so there is no need for VREF
.
Select the VCCO and VREF levels to suit the desired sin-
gle-ended standard according to Table 4.
3. See Table 6 for a listing of the single-ended DCI standards.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling (e.g.,
Common-Mode Rejection) properties of these standards
permit exceptionally high data transfer rates. This section
introduces the differential signaling capabilities of Spartan-3
devices.
Table 5: Differential I/O Standards
VCCO (Volts)
VREF for
Inputs
(Volts)
For
For
Inputs
Signal Standard
LDT_25 (ULVDS_25)
LVDS_25
Outputs
2.5
2.5
2.5
2.5
2.5
2.5
-
-
-
-
-
-
-
-
-
-
-
-
Each device-package combination designates specific I/O
pairs that are specially optimized to support differential
standards. A unique “L-number”, part of the pin name, iden-
tifies the line-pairs associated with each bank (see Module
4: Pinout Descriptions). For each pair, the letters “P” and
“N” designate the true and inverted lines, respectively. For
example, the pin names IO_L43P_7 and IO_L43N_7 indi-
cate the true and inverted lines comprising the line pair L43
on Bank 7. The VCCO lines provide current to the outputs.
The VREF lines are not used. Select the VCCO level to suit
the desired differential standard according to Table 5.
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
Notes:
1. See Table 6 for a listing of the differential DCI standards.
The need to supply VREF and VCCO imposes constraints on
which standards can be used in the same bank. See The
Organization of IOBs into Banks section for additional
guidelines concerning the use of the VCCO and VREF lines.
Table 4: Single-Ended I/O Standards (Values in Volts)
VCCO
Board
Termination
Digitally Controlled Impedance (DCI)
Signal
Standard
For
For
VREF for
When the round-trip delay of an output signal — i.e., from
output to input and back again — exceeds rise and fall
times, it is common practice to add termination resistors to
the line carrying the signal. These resistors effectively
match the impedance of a device’s I/O to the characteristic
impedance of the transmission line, thereby preventing
reflections that adversely affect signal integrity. However,
with the high I/O counts supported by modern devices, add-
ing resistors requires significantly more components and
board area. Furthermore, for some packages — e.g., ball
grid arrays — it may not always be possible to place resis-
tors close to pins.
Outputs Inputs Inputs(1) Voltage (VTT
)
GTL
Note 2
Note 2
1.5
Note 2
0.8
1.2
1.5
0.75
1.5
0.9
0.9
1.8
-
GTLP
Note 2
1
0.75
0.9
0.9
0.9
1.1
-
HSTL_I
-
-
HSTL_III
1.5
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
1.8
-
1.8
-
1.8
-
1.2
1.2
1.5
1.8
2.5
3.3
3.3
3.0
-
1.5
-
-
DCI answers these concerns by providing two kinds of
on-chip terminations: Parallel terminations make use of an
integrated resistor network. Series terminations result from
controlling the impedance of output drivers. DCI actively
adjusts both parallel and series terminations to accurately
match the characteristic impedance of the transmission line.
This adjustment process compensates for differences in I/O
impedance that can result from normal variation in the
ambient temperature, the supply voltage and the manufac-
1.8
-
-
2.5
-
-
3.3
-
-
3.3
-
-
PCI33_3
3.0
-
-
SSTL18_I
1.8
0.9
0.9
DS099-2 (v1.3) August 24, 2004
www.xilinx.com
5
Preliminary Product Specification
XILINX [ XILINX, INC ]
