R
Spartan-3 FPGA Family: Functional Description
of the signal standard selected. The presence of diodes lim-
its the ability of Spartan-3 I/Os to tolerate high signal volt-
ages. The VIN absolute maximum rating in Table 1 in
Module 3: DC and Switching Characteristics specifies the
voltage range that I/Os can tolerate.
DCM
180˚ 0˚
FDDR
Slew Rate Control and Drive Strength
D1
Two options, FAST and SLOW, control the output slew rate.
The FAST option supports output switching at a high rate.
The SLOW option reduces bus transients. These options are
only available when using one of the LVCMOS or LVTTL
standards, which also provide up to seven different levels of
current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. Choos-
ing the appropriate drive strength level is yet another means
to minimize bus transients.
Q1
CLK1
DDR MUX
Q
D2
Table 3 shows the drive strengths that the LVCMOS and
LVTTL standards support. The Fast option is indicated by
appending an "F" attribute after the output buffer symbol
OBUF or the bidirectional buffer symbol IOBUF. The Slow
option appends an "S" attribute. The drive strength in milliam-
peres follows the slew rate attribute. For example,
OBUF_LVCMOS18_S_6 or IOBUF_LVCMOS25_F_16.
Q2
CLK2
DS099-2_02_070303
Table 3: Programmable Output Drive Current
Figure 2: Clocking the DDR Register
Current Drive (mA)
Signal
Standard
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
2
4
6
8
12
16
-
24
-
Pull-Up and Pull-Down Resistors
The optional pull-up and pull-down resistors are intended to
establish High and Low levels, respectively, at unused I/Os.
The pull-up resistor optionally connects each IOB pad to
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
3
3
3
3
3
3
3
3
3
3
-
-
3
3
3
3
-
VCCO. A pull-down resistor optionally connects each pad to
3
3
3
GND. These resistors are placed in a design using the
PULLUP and PULLDOWN symbols in a schematic, respec-
tively. They can also be instantiated as components, set as
constraints or passed as attributes in HDL code. These
resistors can also be selected for all unused I/O using the
Bitstream Generator (BitGen) option UnusedPin. A Low
logic level on HSWAP_EN activates the pull-up resistors on
all I/Os during configuration.
Boundary-Scan Capability
All Spartan-3 IOBs support boundary-scan testing compat-
ible with IEEE 1149.1 standards. See Boundary-Scan
(JTAG) Mode, page 36 for more information.
Keeper Circuit
SelectIO Signal Standards
Each I/O has an optional keeper circuit that retains the last
logic level on a line after all drivers have been turned off.
This is useful to keep bus lines from floating when all con-
nected drivers are in a high-impedance state. This function
is placed in a design using the KEEPER symbol. Pull-up
and pull-down resistors override the keeper circuit.
The IOBs support 17 different single-ended signal stan-
dards, as listed in Table 4. Furthermore, the majority of
IOBs can be used in specific pairs supporting any of six dif-
ferential signal standards, as shown in Table 5. The desired
standard is selected by placing the appropriate I/O library
symbol or component into the FPGA design. For example,
the symbol named IOBUF_LVCMOS15_F_8 represents a
bidirectional I/O to which the 1.5V LVCMOS signal standard
has been assigned. The slew rate and current drive are set
to Fast and 8 mA, respectively.
ESD Protection
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: One diode
extends P-to-N from the pad to VCCO and a second diode
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
Together with placing the appropriate I/O symbol, two exter-
nally applied voltage levels, VCCO and VREF select the
desired signal standard. The VCCO lines provide current to
the output driver. The voltage on these lines determines the
4
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DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
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