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Spartan-3 FPGA Family: Functional Description
According to Figure 1, the clock line OTCLK1 connects the
CK inputs of the upper registers on the output and
three-state paths. Similarly, OTCLK2 connects the CK
inputs for the lower registers on the output and three-state
paths. The upper and lower registers on the input path have
independent clock lines: ICLK1 and ICLK2.
path and ICE does the same for the register pair on the
input path.
The Set/Reset (SR) line entering the IOB is common to all
six registers, as is the Reverse (REV) line.
Each storage element supports numerous options in addi-
tion to the control over signal polarity described in the IOB
Overview section. These are described in Table 2.
The enable line OCE connects the CE inputs of the upper
and lower registers on the output path. Similarly, TCE con-
nects the CE inputs for the register pair on the three-state
Table 2: Storage Element Options
Option Switch
Function
Specificity
FF/Latch
Chooses between an edge-sensitive flip-flop or Independent for each storage element.
a level-sensitive latch
SYNC/ASYNC
Determines whether SR is synchronous or
asynchronous
Independent for each storage element.
SRHIGH/SRLOW Determines whether SR acts as a Set, which
forces the storage element to a logic “1"
Independent for each storage element, except
when using FDDR. In the latter case, the selection
(SRHIGH) or a Reset, which forces a logic “0” for the upper element (OFF1 or TFF2) will apply to
(SRLOW).
both elements.
INIT1/INIT0
In the event of a Global Set/Reset, after
Independent for each storage element, except
configuration or upon activation of the GTS net, when using FDDR. In the latter case, selecting
this switch decides whether to set or reset a INIT0 for one element applies to both elements
storage element. By default, choosing SRLOW (even though INIT1 is selected for the other).
also selects INIT0; choosing SRHIGH also
selects INIT1.
The storage-element-pair on the Three-State path (TFF1
Double-Data-Rate Transmission
and TFF2) can also be combined with a local multiplexer to
form an FDDR primitive. This permits synchronizing the out-
put enable to both the rising and falling edges of a clock.
This DDR operation is realized in the same way as for the
output path.
Double-Data-Rate (DDR) transmission describes the tech-
nique of synchronizing signals to both the rising and falling
edges of the clock signal. Spartan-3 devices use regis-
ter-pairs in all three IOB paths to perform DDR operations.
The pair of storage elements on the IOB’s Output path
(OFF1 and OFF2), used as registers, combine with a spe-
cial multiplexer to form a DDR D-type flip-flop (FDDR). This
primitive permits DDR transmission where output data bits
are synchronized to both the rising and falling edges of a
clock. It is possible to access this function by placing either
an FDDRRSE or an FDDRCPE component or symbol into
the design. DDR operation requires two clock signals (50%
duty cycle), one the inverted form of the other. These sig-
nals trigger the two registers in alternating fashion, as
shown in Figure 2. Commonly, the Digital Clock Manager
(DCM) generates the two clock signals by mirroring an
incoming signal, then shifting it 180 degrees. This approach
ensures minimal skew between the two signals.
The storage-element-pair on the input path (IFF1 and IFF2)
allows an I/O to receive a DDR signal. An incoming DDR
clock signal triggers one register and the inverted clock sig-
nal triggers the other register. In this way, the registers take
turns capturing bits of the incoming DDR data signal.
Aside from high bandwidth data transfers, DDR can also be
used to reproduce, or “mirror”, a clock signal on the output.
This approach is used to transmit clock and data signals
together. A similar approach is used to reproduce a clock
signal at multiple outputs. The advantage for both
approaches is that skew across the outputs will be minimal.
DS099-2 (v1.3) August 24, 2004
www.xilinx.com
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Preliminary Product Specification
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