R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Speed Grade
Table 43: Sample Window
Description
Sampling Error at Receiver Pins(1)
Symbol
Device
XC2V40
–6
–5
500
500
500
500
500
500
500
500
500
500
TBD
–4
Units
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TSAMP
XC2V80
ps
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
ps
ps
ps
ps
ps
ps
ps
ps
ps
Notes:
1. This parameter indicates the total sampling error of Virtex-II DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - TDCD_CLK180
- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree skew.
Table 44: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
Speed Grade
Description
Symbol
Device
–6
–5
–4
Units
Data Input Set-Up and Hold Times Relative to a Forwarded
Clock Input Pin, Using DCM and Global Clock Buffer.
For situations where clock and data inputs conform to
different standards, adjust the setup and hold values
accordingly using the values shown in IOB Input Switching
Characteristics Standard Adjustments, page 11.
No Delay
XC2V40
XC2V80
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPSDCM
TPHDCM
/
Global Clock and IFF with DCM
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
TBD
TBD
0.2/0.5
TBD
TBD
0.2/0.5
TBD
0.2/0.6
TBD
Notes:
1. IFF = Input Flip-Flop
2. The timing values were measured using the fine-phase adjustment feature of the DCM.
3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
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XILINX [ XILINX, INC ]
