R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Miscellaneous Timing Parameters
Table 38: Miscellaneous Timing Parameters
Constraints
Description
Symbol
FCLKIN
Speed Grade
–5
Units
–6
–4
Time Required to Achieve LOCK
Using DLL outputs(1)
LOCK_DLL
LOCK_DLL_60
> 60MHz
20.0
25.0
50.0
90.0
120.0
10.0
10.0
20.0
25.0
50.0
90.0
120.0
10.0
10.0
20.0
25.0
50.0
90.0
120.0
10.0
10.0
µs
µs
µs
µs
µs
ms
ms
LOCK_DLL_50_60
LOCK_DLL_40_50
LOCK_DLL_30_40
LOCK_DLL_24_30
LOCK_FX_MIN
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
24 - 30 MHz
Using CLKFX outputs
LOCK_FX_MAX
Additional lock time with
fine-phase shifting
LOCK_DLL_FINE_SHIFT
50.0
50.0
50.0
µs
Fine-Phase Shifting
Absolute shifting range
Delay Lines
FINE_SHIFT_RANGE
10.0
10.0
10.0
ns
Tap delay resolution
DCM_TAP_MIN
DCM_TAP_MAX
30.0
60.0
30.0
60.0
30.0
60.0
ps
ps
Notes:
1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
Frequency Synthesis
Table 39: Frequency Synthesis
Attribute
Min
2
Max
32
CLKFX_MULTIPLY
CLKFX_DIVIDE
1
32
Parameter Cross Reference
Table 40: Parameter Cross Reference
Libraries Guide
Data Sheet
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
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