R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Table 30: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Speed Grade
Description
Symbol
Device
–6
–5
–4
Units
LVTTL Global Clock Input to Output delay
using Output flip-flop, 12 mA, Fast Slew
Rate, with DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard Adjustments, page 14.
XC2V40
XC2V80
1.10
1.10
1.10
1.10
1.10
1.10
1.10
1.19
1.19
1.64
1.64
1.28
1.28
1.28
1.28
1.28
1.28
1.28
1.38
1.38
1.88
1.88
1.48
1.48
1.48
1.48
1.48
1.48
1.48
1.59
1.59
2.17
2.17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Clock and OFF with DCM
TICKOFDCM
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with test setup shwon in Figure 1. For other I/O standards and different loads, see
Table 18.
DS031-3 (v3.0) August 1, 2003
Product Specification
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