R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Block SelectRAM Switching Characteristics
Table 27: Block SelectRAM Switching Characteristics
Speed Grade
Description
Sequential Delays
Symbol
–6
–5
–4
Units
2.10
2.31
2.65
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
ADDR inputs
T
ns, Max
BCKO
0.29/ 0.00
0.29/ 0.00
0.95/–0.46
1.31/–0.71
0.57/–0.19
0.32/ 0.00
0.32/ 0.00
1.04/–0.50
1.44/–0.78
0.63/–0.21
0.36/ 0.00
0.36/ 0.00
1.20/–0.58
1.65/–0.90
0.72/–0.25
T
/T
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
BACK BCKA
DIN inputs
T
/T
BDCK BCKD
EN input
T
/T
BECK BCKE
RST input
T
/T
BRCK BCKR
WEN input
T
/T
BWCK BCKW
Clock CLK
1.17
1.17
1.29
1.29
1.48
1.48
Minimum Pulse Width, High
Minimum Pulse Width, Low
T
ns, Min
ns, Min
BPWH
T
BPWL
TBUF Switching Characteristics
Table 28: TBUF Switching Characteristics
Speed Grade
Description
Combinatorial Delays
Symbol
–6
–5
–4
Units
0.45
0.44
0.44
0.50
0.48
0.48
0.58
0.55
0.55
IN input to OUT output
T
ns, Max
ns, Max
ns, Max
IO
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
T
OFF
T
ON
JTAG Test Access Port Switching Characteristics
Table 29: JTAG Test Access Port Switching Characteristics
Description
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Symbol
Units
T
5.5
0.0
ns, Min
ns, Min
TAPTK
T
TCKTAP
TCKTDO
T
10.0
33
ns, Max
MHz, Max
F
TCK
DS031-3 (v3.0) August 1, 2003
Product Specification
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