R
Virtex™-II Platform FPGAs: Detailed Description
Note that CLK2X and CLK2X180 are not available in
high-frequency mode.
Phase Shifting
The DCM provides additional control over clock skew
through either coarse or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
shifting. For more information on DCM features, see the
Virtex-II User Guide.
Table 21 lists fine-phase shifting control pins, when used in
variable mode.
Table 21: Fine-Phase Shifting Control Pins
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.
Control Pin
PSINCDEC
PSEN
Direction
Function
in
in
Increment or decrement
Enable phase shift
Clock for phase shift
Active when completed
In variable mode, the PHASE_SHIFT value can also be
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active. Figure 46 illustrates the effects of fine-phase
PSCLK
in
PSDONE
out
CLKIN
CLKOUT_PHASE_SHIFT
= NONE
CLKFB
CLKIN
CLKFB
CLKOUT_PHASE_SHIFT
= FIXED
(PS/256) x PERIOD
(PS negative)
(PS/256) x PERIOD
(PS positive)
CLKIN
CLKIN
CLKIN
CLKFB
CLKOUT_PHASE_SHIFT
= VARIABLE
(PS/256) x PERIOD
(PS negative)
(PS/256) x PERIOD
CLKIN
CLKIN
(PS positive)
DS031_48_101201
Figure 46: Fine-Phase Shifting Effects
Two separate components of the phase shift range must be
understood:
Absolute range (variable mode) = FINE_SHIFT_RANGE/2
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the PHASE_SHIFT value never changes after configu-
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
•
•
PHASE_SHIFT attribute range
FINE_SHIFT_RANGE DCM timing parameter range
The PHASE_SHIFT attribute is the numerator in the following
equation:
Phase Shift (ns) = (PHASE_SHIFT/256) * PERIOD
CLKIN
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the FINE_SHIFT_RANGE component, which represents
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under DCM Tim-
ing Parameters in Module 3.
Taking both of these components into consideration, the fol-
lowing are some usage examples:
•
If PERIOD
= 2 * FINE_SHIFT_RANGE, then
CLKIN
PHASE_SHIFT in fixed mode is limited to 128, and in
variable mode it is limited to 64.
•
If PERIOD
= FINE_SHIFT_RANGE, then
CLKIN
Absolute range (fixed mode) = FINE_SHIFT_RANGE
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
31
XILINX [ XILINX, INC ]
