R
Virtex™-II Platform FPGAs: Detailed Description
In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.
BUFGMUX
BUFGMUX can switch between two unrelated, even asyn-
chronous clocks. Basically, a Low on S selects the I0 input,
a High on S selects the I1 input. Switching from one clock to
the other is done in such a way that the output High and Low
time is never shorter than the shortest High or Low time of
either input clock. As long as the presently selected clock is
High, any level change of S has no effect .
To reduce power consumption, any unused clock branches
remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to mul-
tiplex between two independent clock inputs (BUFGMUX).
BUFGMUX
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in Figure 41.
I0
O
I1
BUFG
I
O
S
DS031_63_112900
DS031_61_101200
Figure 43: Virtex-II BUFGMUX Function
Figure 41: Virtex-II BUFG Function
If the presently selected clock is Low while S changes, or if
it goes Low after S has changed, the output is kept Low until
the other ("to-be-selected") clock has made a transition
from High to Low. At that instant, the new clock starts driv-
ing the output.
The Virtex-II global clock buffer BUFG can also be config-
ured as a clock enable/disable circuit (Figure 42), as well as
a two-input clock multiplexer (Figure 43). A functional
description of these two options is provided below. Each of
them can be used in either of two modes, selected by con-
figuration: rising clock edge or falling clock edge.
The two clock inputs can be asynchronous with regard to
each other, and the S input can change at any time, except
for a short setup time prior to the rising edge of the presently
selected clock; that is, prior to the rising edge of the
BUFGMUX output O. Violating this setup time requirement
can result in an undefined runt pulse output.
This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE or S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX prim-
itives. The falling clock edge option uses the BUFGCE_1
and BUFGMUX_1 primitives.
All Virtex-II devices have 16 global clock multiplexer buffers.
Figure 44 shows a switchover from CLK0 to CLK1.
BUFGCE
Wait for Low
If the CE input is active (High) prior to the incoming rising
clock edge, this Low-to-High-to-Low clock pulse passes
through the clock buffer. Any level change of CE during the
incoming clock High time has no effect.
S
CLK0
Switch
CLK1
BUFGCE
OUT
I
O
CE
DS031_62_101200
DS031_46_112900
Figure 42: Virtex-II BUFGCE Function
Figure 44: Clock Multiplexer Waveform Diagram
If the CE input is inactive (Low) prior to the incoming rising
clock edge, the following clock pulse does not pass through
the clock buffer, and the output stays Low. Any level change
of CE during the incoming clock High time has no effect. CE
must not change during a short setup window just prior to
the rising clock edge on the BUFGCE input I. Violating this
setup time requirement can result in an undefined runt
pulse output.
•
•
•
The current clock is CLK0.
S is activated High.
If CLK0 is currently High, the multiplexer waits for CLK0
to go Low.
•
•
•
Once CLK0 is Low, the multiplexer output stays Low
until CLK1 transitions High to Low.
When CLK1 transitions from High to Low, the output
switches to CLK1.
No glitches or short pulses can appear on the output.
DS031-2 (v3.0) August 1, 2003
Product Specification
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