R
Virtex™-II Platform FPGAs: Detailed Description
number of CLBs in a column divided by four. Column loca-
tions are shown in Table 17.
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports
with the control signals described in Table 16. All control
inputs including the clock have an optional inversion.
Table 17: SelectRAM Memory Floor Plan
SelectRAM Blocks
Table 16: Control Functions
Device
Columns
Per Column
Total
4
Control Signal
Function
XC2V40
2
2
4
4
4
4
4
6
6
6
6
2
CLK
EN
Read and Write Clock
XC2V80
4
8
Enable affects Read, Write, Set, Reset
Write Enable
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
6
24
WE
SSR
8
32
Set DO register to SRVAL (attribute)
10
12
14
16
20
24
28
40
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
48
56
96
120
144
168
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
SelectRAM Blocks
SelectRAM Blocks
SelectRAM Blocks
ds031_38_101000
Figure 34: Block SelectRAM (2-column, 4-column, and 6-column)
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
25
XILINX [ XILINX, INC ]
