R
Virtex™-II Platform FPGAs: Detailed Description
Multiplexers
Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in Figure 23.
Each CLB element has two MUXF6 multiplexers, one
MUXF7 multiplexer and one MUXF8 multiplexer. Examples
of multiplexers are shown in the Virtex-II User Guide. Any
LUT can implement a 2:1 multiplexer.
Virtex-II function generators and associated multiplexers
can implement the following:
•
•
•
•
4:1 multiplexer in one slice
8:1 multiplexer in two slices
16:1 multiplexer in one CLB element (4 slices)
32:1 multiplexer in two CLB elements (8 slices)
MUXF8 combines
the two MUXF7 outputs
(Two CLBs)
G
F
Slice S3
MUXF6 combines the two MUXF5
outputs from slices S2 and S3
G
F
Slice S2
MUXF7 combines the two MUXF6
outputs from slices S0 and S2
G
Slice S1
F
MUXF6 combines the two MUXF5
outputs from slices S0 and S1
G
F
Slice S0
CLB
DS031_08_100201
Figure 23: MUXF5 and MUXFX multiplexers
Fast Lookahead Carry Logic
be used to cascade function generators for implementing
wide logic functions.
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the Figure 24.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND (MULT_AND) gate (shown in Figure 16)
improves the efficiency of multiplier implementation.
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedi-
cated carry path and carry multiplexer (MUXCY) can also
DS031-2 (v3.0) August 1, 2003
Product Specification
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