R
Virtex™-II Platform FPGAs: Detailed Description
COUT
SHIFTIN
ORCY
SOPIN
SOPOUT
0
Dual-Port
Shift-Reg
YBMUX
YB
MUXCY
1
A4
A3
A2
A1
WG4
WG3
WG2
WG1
G4
G3
G2
1
0
LUT
RAM
ROM
G1
D
GYMUX
Y
WG4
WG3
WG2
WG1
G
DY
MC15
DI
XORG
FF
LATCH
WS
ALTDIG
DYMUX
CE
D
Q
G2
PROD
G1
Q
Y
MULTAND
CE
CLK CK
CYOG
BY
1
0
SR REV
BY
SLICEWE[2:0]
WSG
SR
SHIFTOUT
WE[2:0]
WE
DIG
CLK
MUXCY
1
0
WSF
CE
CLK
SR
Shared between
x & y Registers
CIN
DS031_01_112502
Figure 16: Virtex-II Slice (Top Half)
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
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