Spartan-IIE FPGA Family:
Introduction and Ordering
Information
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DS077-1 (v2.3) June 18, 2008
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Product Specification
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Fast interfaces to external RAM
Introduction
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Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
Low-power segmented routing architecture
Dedicated carry logic for high-speed arithmetic
Efficient multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
The Spartan®-IIE Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
seven-member family offers densities ranging from 50,000
to 600,000 system gates, as shown in Table 1. System per-
formance is supported beyond 200 MHz.
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Features include block RAM (to 288K bits), distributed RAM
(to 221,184 bits), 19 selectable I/O standards, and four
DLLs (Delay-Locked Loops). Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
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Eliminate clock distribution delay
Multiply, divide, or phase shift
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Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
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Versatile I/O and packaging
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Pb-free package options
Low-cost packages available in all densities
Family footprint compatibility in common packages
19 high-performance interface standards
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Up to 205 differential I/O pairs that can be input,
output, or bidirectional
Hot swap I/O (CompactPCI friendly)
LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
LVDS and LVPECL differential I/O
Features
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Second generation ASIC replacement technology
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Densities as high as 15,552 logic cells with up to
600,000 system gates
Streamlined features based on Virtex®-E FPGA
architecture
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Core logic powered at 1.8V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx® ISE® development
system
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Unlimited in-system reprogrammability
Very low cost
Cost-effective 0.15 micron technology
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Fully automatic mapping, placement, and routing
Integrated with design entry and verification tools
Extensive IP library including DSP functions and
soft processors
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System level features
SelectRAM™ hierarchical memory:
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16 bits/LUT distributed RAM
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Configurable 4K-bit true dual-port block RAM
Table 1: Spartan-IIE FPGA Family Members
Typical
System Gate Range
(Logic and RAM)
CLB
Array
(R x C)
Maximum
Available
User I/O(1)
Maximum
Differential
I/O Pairs
Logic
Cells
Total
CLBs
Distributed BlockRAM
Device
RAM Bits
Bits
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
1,728
2,700
3,888
5,292
6,912
10,800
15,552
23,000 - 50,000
37,000 - 100,000
52,000 - 150,000
71,000 - 200,000
93,000 - 300,000
145,000 - 400,000
210,000 - 600,000
16 x 24
20 x 30
24 x 36
28 x 42
32 x 48
40 x 60
48 x 72
384
600
182
202
265
289
329
410
514
83
24,576
32K
86
38,400
40K
864
114
120
120
172
205
55,296
48K
1,176
1,536
2,400
3,456
75,264
56K
98,304
64K
153,600
221,184
160K
288K
Notes:
1. User I/O counts include the four global clock/user input pins. See details in Table 2, page 5
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Product Specification
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