R
XC1800 Series of In-System Programmable Configuration PROMs
interconnected. After the last bit from the first PROM is
read, the next clock signal to the PROM asserts its CEO
output Low and disables its DATA line. The second PROM
recognizes the Low level on its CE input and enables its
DATA output. See
Figure 5.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the PROM OE/RESET pin
goes Low.
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of DIN.
September 17, 1999 (Version 1.3)
9
XILINX [ XILINX, INC ]
