R
XC1800 Series of In-System Programmable Configuration PROMs
Vcc
OPTIONAL
OUT
D
Daisy-chained
FPGAs with
Different
Configurations
FPGA
OPTIONAL
Slave FPGAs
with Identical
Configurations
MODES
Vcc
Vcco
V
V
CCO
CC
DATA
DATA
CLK
DIN
Cascaded
PROM
CLK
CCLK
DONE
INIT
FIRST
PROM
CEO
CE
CE
OE/RESET
CF
OE/RESET
PROGRAM
(Low Resets the Address Pointer)
Master Serial Mode
I/O*
I/O*
3.3V
Vcco
Vcc
CC
CS
WRITE
VIRTEX
Select MAP
M0
M1
M2
4.7k
4.7k
External Osc
3.3V
4.7K
V
V
CCO
NC
BUSY
DONE
XC18xx
CLK
CCLK
D0-D7
8
D0-D7
CE
OE/RESET
PROGRAM
CEO
CF
INIT
Virtex Select MAP Mode
To Additional
Optional
Vcc
Daisy-Chained
Devices
M0
M1
DOUT
M0
M1
Vcco
Vcc
CS1
CS1
Optional
Daisy-Chained
Spartan XL
DOUT
Vcc
4k
Spartan XL
V
CC
V
CCO
8
CEO
D0-D7
CF
D0-D7
D0-D7
XC18xx
DONE
PROGRAM
INIT
PROGRAM DONE
CE
OE/RESET
CLK
INIT
CCLK
CCLK
To Additional
Optional
Daisy-Chained
Devices
CCLK
Spartan XL Express Mode
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
Figure 5: (a) Master Serial Mode (b) Virtex Select MAP Mode (c) Spartan XL Express Mode
10
September 17, 1999 (Version 1.3)
XILINX [ XILINX, INC ]
